sh4.inc

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· INC 代码 · 共 1,099 行 · 第 1/4 页

BSC_PCR_A6TED_12:			.equ	h'0180	; Area 6 has 12 wait inserted 
BSC_PCR_A6TED_15:			.equ 	h'01c0	; Area 6 has 15 wait inserted 

BSC_PCR_A5TEH: 				.equ	h'0038	; PCMCIA area 5 negation address delay mask 
BSC_PCR_A5TEH_0:			.equ	h'0000	; Area 5 has 0 wait inserted 
BSC_PCR_A5TEH_1:			.equ	h'0008	; Area 5 has 1 wait inserted 
BSC_PCR_A5TEH_2:			.equ	h'0010	; Area 5 has 2 wait inserted 
BSC_PCR_A5TEH_3:			.equ	h'0018	; Area 5 has 3 wait inserted 
BSC_PCR_A5TEH_6:			.equ	h'0020	; Area 5 has 6 wait inserted 
BSC_PCR_A5TEH_9:			.equ	h'0028	; Area 5 has 9 wait inserted 
BSC_PCR_A5TEH_12:			.equ 	h'0030	; Area 5 has 12 wait inserted 
BSC_PCR_A5TEH_15:			.equ	h'0038	; Area 5 has 15 wait inserted 

BSC_PCR_A6TEH: 				.equ	h'0007	; PCMCIA area 6 negation address delay mask 
BSC_PCR_A6TEH_0:			.equ	h'0000	; Area 6 has 0 wait inserted 
BSC_PCR_A6TEH_1:			.equ	h'0001	; Area 6 has 1 wait inserted 
BSC_PCR_A6TEH_2:			.equ	h'0002	; Area 6 has 2 wait inserted 
BSC_PCR_A6TEH_3:			.equ	h'0003	; Area 6 has 3 wait inserted 
BSC_PCR_A6TEH_6:			.equ	h'0004	; Area 6 has 6 wait inserted 
BSC_PCR_A6TEH_9:			.equ	h'0005	; Area 6 has 9 wait inserted 
BSC_PCR_A6TEH_12:			.equ	h'0006	; Area 6 has 12 wait inserted 
BSC_PCR_A6TEH_15:			.equ 	h'0007	; Area 6 has 15 wait inserted 

;; Synchronous DRAM Mode Register(SDMR)  

; Values that will be written to many of the following registers must be ORed
; with their corresponding *_*_COOKIE value before writing the register.
; Otherwise, the hardware will reject (ignore) the write.

; RTCSR: Refresh timer control/status register (refresh cycle, interrupt enable,
; and the interrupt's cycle).

BSC_SDMR2_COOKIE:			.equ	h'FF900000	; OR with new value before writing
BSC_SDMR3_COOKIE:			.equ	h'FF940000	; OR with new value before writing

BSC_SDMR3_190:				.equ	h'00000190	; 32bit, LMODE=3, WT=0, BL=4, 
BSC_SDMR3_110:				.equ	h'00000110	; 32bit, LMODE=3, WT=0, BL=4, 

BSC_RTCSR_COOKIE:			.equ	h'a500	; OR with new value before writing
BSC_RTCSR_CMF:				.equ	h'0080	; Predicate, RTCNT == RTCOR
BSC_RTCSR_CMIE:				.equ	h'0040	; Enable an interrupt via CMF

BSC_RTCSR_CKS:				.equ	h'0038	; Clock select mask
BSC_RTCSR_CKS_DISABLE:		.equ	h'0000	; Disable clock input
BSC_RTCSR_CKS_4:			.equ	h'0008	; CKIO/4
BSC_RTCSR_CKS_16:			.equ	h'0010	; CKIO/16
BSC_RTCSR_CKS_64:			.equ	h'0018	; CKIO/64
BSC_RTCSR_CKS_256:			.equ	h'0020	; CKIO/256
BSC_RTCSR_CKS_1024:			.equ	h'0028	; CKIO/1024
BSC_RTCSR_CKS_2048:			.equ	h'0030	; CKIO/2048
BSC_RTCSR_CKS_4096:			.equ	h'0038	; CKIO/4096

BSC_RTCSR_OVF:				.equ	h'0004	; RFCR has exceeded count limit in LMTS
BSC_RTCSR_OVIE:				.equ	h'0002	; Enable an interrupt via OVF
BSC_RTCSR_LMTS:				.equ	h'0001	; Count limit: 0 => 1024, 1 => 512	

; RTCNT: Refresh timer counter.

BSC_RTCNT_COOKIE:			.equ	h'a500	; OR with new value before writing
BSC_RTCNT_COUNT_FF:			.equ	h'00ff	; Refresh timer counter mask
BSC_RTCNT_COUNT_00:			.equ	h'0000	; Refresh timer counter mask

; RTCOR: Refresh time constant register.

BSC_RTCOR_COOKIE:			.equ	h'a500	; OR with new value before writing
BSC_RTCOR_COUNT:			.equ	h'00ff	; Refresh time constant mask

; RFCR: Refresh count register.

BSC_RFCR_COOKIE:			.equ	h'a400	; OR with new value before writing
BSC_RFCR_COUNT:				.equ	h'03ff	; Refresh count mask

;
; DMAC registers
;

DMAC_REGBASE				.equ	h'FFA00000
DMAC_REGSIZE				.equ	h'0044

DMAC_SAR0_OFFSET			.equ	h'0000
DMAC_DAR0_OFFSET			.equ	h'0004
DMAC_DMATCR0_OFFSET			.equ	h'0008
DMAC_CHCR0_OFFSET			.equ	h'000C

DMAC_SAR1_OFFSET			.equ	h'0010
DMAC_DAR1_OFFSET			.equ	h'0014
DMAC_DMATCR1_OFFSET			.equ	h'0018
DMAC_CHCR1_OFFSET			.equ	h'001C

DMAC_SAR2_OFFSET			.equ	h'0020
DMAC_DAR2_OFFSET			.equ	h'0024
DMAC_DMATCR2_OFFSET			.equ	h'0028
DMAC_CHCR2_OFFSET			.equ	h'002C

DMAC_SAR3_OFFSET			.equ	h'0030
DMAC_DAR3_OFFSET			.equ	h'0034
DMAC_DMATCR3_OFFSET			.equ	h'0038
DMAC_CHCR3_OFFSET			.equ	h'003C

DMAC_DMAOR_OFFSET			.equ	h'0040
					
DMAC_SAR0					.equ	(DMAC_REGBASE + DMAC_SAR0_OFFSET)
DMAC_DAR0					.equ	(DMAC_REGBASE + DMAC_DAR0_OFFSET)
DMAC_DMATCR0				.equ	(DMAC_REGBASE + DMAC_DMATCR0_OFFSET)
DMAC_CHCR0					.equ	(DMAC_REGBASE + DMAC_CHCR0_OFFSET)

DMAC_SAR1					.equ	(DMAC_REGBASE + DMAC_SAR1_OFFSET)
DMAC_DAR1					.equ	(DMAC_REGBASE + DMAC_DAR1_OFFSET)
DMAC_DMATCR1				.equ	(DMAC_REGBASE + DMAC_DMATCR1_OFFSET)
DMAC_CHCR1					.equ	(DMAC_REGBASE + DMAC_CHCR1_OFFSET)

DMAC_SAR2					.equ	(DMAC_REGBASE + DMAC_SAR2_OFFSET)
DMAC_DAR2					.equ	(DMAC_REGBASE + DMAC_DAR2_OFFSET)
DMAC_DMATCR2				.equ	(DMAC_REGBASE + DMAC_DMATCR2_OFFSET)
DMAC_CHCR2					.equ	(DMAC_REGBASE + DMAC_CHCR2_OFFSET)

DMAC_SAR3					.equ	(DMAC_REGBASE + DMAC_SAR3_OFFSET)
DMAC_DAR3					.equ	(DMAC_REGBASE + DMAC_DAR3_OFFSET)
DMAC_DMATCR3				.equ	(DMAC_REGBASE + DMAC_DMATCR3_OFFSET)
DMAC_CHCR3					.equ	(DMAC_REGBASE + DMAC_CHCR3_OFFSET)

DMAC_DMAOR					.equ	(DMAC_REGBASE + DMAC_DMAOR_OFFSET)

;	DMA channel control register (DMAC_CHCR0 to 3)

DMAC_CHCR_SSA_RESERVED		.equ	h'00000000
DMAC_CHCR_SSA_DYNAMIC_IO	.equ	h'20000000
DMAC_CHCR_SSA_8_IO			.equ	h'40000000
DMAC_CHCR_SSA_16_IO			.equ	h'60000000
DMAC_CHCR_SSA_8_COMM		.equ	h'80000000
DMAC_CHCR_SSA_16_COMM		.equ	h'A0000000
DMAC_CHCR_SSA_8_ATTR		.equ	h'C0000000
DMAC_CHCR_SSA_16_ATTR		.equ	h'E0000000

DMAC_CHCR_STC_CS5			.equ	h'00000000
DMAC_CHCR_STC_CS6			.equ	h'10000000

DMAC_CHCR_DSA_RESERVED		.equ	h'00000000
DMAC_CHCR_DSA_DYNAMIC_IO	.equ	h'02000000
DMAC_CHCR_DSA_8_IO			.equ	h'04000000
DMAC_CHCR_DSA_16_IO			.equ	h'06000000
DMAC_CHCR_DSA_8_COMM		.equ	h'08000000
DMAC_CHCR_DSA_16_COMM		.equ	h'0A000000
DMAC_CHCR_DSA_8_ATTR		.equ	h'0C000000
DMAC_CHCR_DSA_16_ATTR		.equ	h'0E000000

DMAC_CHCR_DTC_CS5			.equ	h'00000000
DMAC_CHCR_DTC_CS6			.equ	h'01000000

DMAC_CHCR_DS_LOW_LEVEL		.equ	h'00000000
DMAC_CHCR_DS_FALLING_EDGE	.equ	h'00080000

DMAC_CHCR_RL_ACTIVE_HIGH	.equ	h'00000000
DMAC_CHCR_RL_ACTIVE_LOW		.equ	h'00040000

DMAC_CHCR_AM_READ_CYCLE		.equ	h'00000000
DMAC_CHCR_AM_WRITE_CYCLE	.equ	h'00020000

DMAC_CHCR_AL_ACTIVE_HIGH	.equ	h'00000000
DMAC_CHCR_AL_ACTIVE_LOW		.equ	h'00010000

DMAC_CHCR_DM_FIXED			.equ	h'00000000
DMAC_CHCR_DM_INCREMENTED	.equ	h'00004000
DMAC_CHCR_DM_DECREMENTED	.equ	h'00008000

DMAC_CHCR_SM_FIXED			.equ	h'00000000
DMAC_CHCR_SM_INCREMENTED	.equ	h'00001000
DMAC_CHCR_SM_DECREMENTED	.equ	h'00002000

DMAC_CHCR_RS_EX_DAM			.equ	h'00000000
DMAC_CHCR_RS_EX_SAM_EAS_ED	.equ	h'00000200
DMAC_CHCR_RS_EX_SAM_ED_EAS	.equ	h'00000300
DMAC_CHCR_RS_AUTO_EAS_EAS	.equ	h'00000400
DMAC_CHCR_RS_AUTO_EAS_OCP	.equ	h'00000500
DMAC_CHCR_RS_AUTO_OCP_EAS	.equ	h'00000600
DMAC_CHCR_RS_SCI1_EMPTY		.equ	h'00000800
DMAC_CHCR_RS_SCI1_FULL		.equ	h'00000900
DMAC_CHCR_RS_SCI2_EMPTY		.equ	h'00000A00
DMAC_CHCR_RS_SCI2_FULL		.equ	h'00000B00
DMAC_CHCR_RS_TMU2_EAS_EAS	.equ	h'00000C00
DMAC_CHCR_RS_TMU2_EAS_OCP	.equ	h'00000D00
DMAC_CHCR_RS_TMU2_OCP_EAS	.equ	h'00000E00

DMAC_CHCR_TM_CYCLE_STEAL	.equ	h'00000000
DMAC_CHCR_TM_BURST			.equ	h'00000080

DMAC_CHCR_TS_64				.equ	h'00000000
DMAC_CHCR_TS_8				.equ	h'00000010
DMAC_CHCR_TS_16				.equ	h'00000020
DMAC_CHCR_TS_32				.equ	h'00000030
DMAC_CHCR_TS_32_BT			.equ	h'00000040

DMAC_CHCR_IE_NOT_GENARATED	.equ	h'00000000
DMAC_CHCR_IE_GENERATED		.equ	h'00000004

DMAC_CHCR_TE_DMATCR_INCOMP	.equ	h'00000000
DMAC_CHCR_TE_DMATCR_COMP	.equ	h'00000002

DMAC_CHCR_DE_DISABLED		.equ	h'00000000
DMAC_CHCR_DE_ENABLED		.equ	h'00000001

DMAC_DMAOR_DDT				.equ	h'00008000
DMAC_DMAOR_PR00				.equ	h'00000000
DMAC_DMAOR_PR01				.equ	h'00000100
DMAC_DMAOR_PR10				.equ	h'00000200
DMAC_DMAOR_PR11				.equ	h'00000300
DMAC_DMAOR_AE				.equ	h'00000004
DMAC_DMAOR_NMFI				.equ	h'00000002
DMAC_DMAOR_DME				.equ	h'00000001

;
; Clock Pulse Generator registers.
;

CPG_REGBASE					.equ	h'FFC00000	; Frequency control register
CPG_REGSIZE					.equ	h'0014

CPG_FRQCR_OFFSET			.equ	h'0000		; Frequency control register
CPG_STBCR_OFFSET			.equ	h'0004		; Stanby control register
CPG_WTCNT_OFFSET			.equ	h'0008		; Watchdog timer counter
CPG_WTCSR_OFFSET			.equ	h'000C		; Watchdog timer control/status register
CPG_STBCR2_OFFSET			.equ	h'0010		; Stanby control register 2

CPG_FRQCR					.equ	(CPG_REGBASE + CPG_FRQCR_OFFSET)
CPG_STBCR					.equ	(CPG_REGBASE + CPG_STBCR_OFFSET)
CPG_WTCNT					.equ	(CPG_REGBASE + CPG_WTCNT_OFFSET)
CPG_WTCSR					.equ	(CPG_REGBASE + CPG_WTCSR_OFFSET)
CPG_STBCR2					.equ	(CPG_REGBASE + CPG_STBCR2_OFFSET)

; Frequency control register.

CPG_FRQCR_CKOEN:			.equ	h'0800	; Clock enable
CPG_FRQCR_PLL1EN:			.equ	h'0400	; PLL circuit 1 enable
CPG_FRQCR_PLL2EN:			.equ	h'0200	; PLL circuit 2 enable

CPG_FRQCR_IFC:				.equ	h'01c0	; Internal clock freq divider mask
CPG_FRQCR_IFC_1:			.equ	h'0000	; /1
CPG_FRQCR_IFC_2:			.equ	h'0040	; /2
CPG_FRQCR_IFC_3:			.equ	h'0080	; /3
CPG_FRQCR_IFC_4:			.equ	h'00c0	; /4
CPG_FRQCR_IFC_6:			.equ	h'0100	; /6
CPG_FRQCR_IFC_8:			.equ	h'0140	; /8

CPG_FRQCR_BFC:				.equ	h'0038	; Bus clock frequency division ratio mask
CPG_FRQCR_BFC_1:			.equ	h'0000	; /1
CPG_FRQCR_BFC_2:			.equ	h'0008	; /2
CPG_FRQCR_BFC_3:			.equ	h'0010	; /3
CPG_FRQCR_BFC_4:			.equ	h'0018	; /4
CPG_FRQCR_BFC_6:			.equ	h'0020	; /6
CPG_FRQCR_BFC_8:			.equ	h'0028	; /8

CPG_FRQCR_PFC:				.equ	h'0007	; Peripheral clock freq divider 2 rate mask
CPG_FRQCR_PFC_2:			.equ	h'0000	; /2
CPG_FRQCR_PFC_3:			.equ	h'0001	; /3
CPG_FRQCR_PFC_4:			.equ	h'0002	; /4
CPG_FRQCR_PFC_6:			.equ	h'0003	; /6
CPG_FRQCR_PFC_8:			.equ	h'0004	; /8	

; Stanby control register

CPG_STBCR_STBY:				.equ	h'80	; Standby
CPG_STBCR_PHZ:				.equ	h'40	; Peripheral module pin high impedance
CPG_STBCR_PPU:				.equ	h'20	; Peripheral moduke pin pull up
CPG_STBCR_MSTP4:			.equ	h'10	; Module standby 4 (DMAC clock on/off)
CPG_STBCR_MSTP3:			.equ	h'08	; Module standby 3 (SCIF clock on/off)
CPG_STBCR_MSTP2:			.equ	h'04	; Module standby 2 (TMU clock on/off)
CPG_STBCR_MSTP1:			.equ	h'02	; Module standby 1 (RTC clock on/off)
CPG_STBCR_MSTP0:			.equ	h'01	; Module standby 0 (SCI clock on/off)

; Watchdog timer counter.

CPG_WTCNT_COOKIE:			.equ	h'5a00	; OR with new value before writing
CPG_WTCNT_COUNT:			.equ	h'00ff	; Watchdog timer counter mask

; Watchdog timer control/status register.