sh4.inc
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· INC 代码 · 共 1,099 行 · 第 1/4 页
INC
1,099 行
BSC_WCR2_A5W_12: .equ h'03000000 ; Area 5 has 12 wait states
BSC_WCR2_A5W_15: .equ h'03800000 ; Area 5 has 15 wait states
BSC_WCR2_A5B: .equ h'00700000 ; Area 5 burst sycle mask
BSC_WCR2_A5B_0: .equ h'00000000 ; Area 5 has 0 states per data transfer
BSC_WCR2_A5B_1: .equ h'00100000 ; Area 5 has 1 states per data transfer
BSC_WCR2_A5B_2: .equ h'00200000 ; Area 5 has 2 states per data transfer
BSC_WCR2_A5B_3: .equ h'00300000 ; Area 5 has 3 states per data transfer
BSC_WCR2_A5B_4: .equ h'00400000 ; Area 5 has 4 states per data transfer
BSC_WCR2_A5B_5: .equ h'00500000 ; Area 5 has 5 states per data transfer
BSC_WCR2_A5B_6: .equ h'00600000 ; Area 5 has 6 states per data transfer
BSC_WCR2_A5B_7: .equ h'00700000 ; Area 5 has 7 states per data transfer
BSC_WCR2_A4W: .equ h'000e0000 ; Area 4 wait state mask
BSC_WCR2_A4W_0: .equ h'00000000 ; Area 4 has 0 wait states
BSC_WCR2_A4W_1: .equ h'00020000 ; Area 4 has 1 wait states
BSC_WCR2_A4W_2: .equ h'00040000 ; Area 4 has 2 wait states
BSC_WCR2_A4W_3: .equ h'00060000 ; Area 4 has 3 wait states
BSC_WCR2_A4W_6: .equ h'00080000 ; Area 4 has 6 wait states
BSC_WCR2_A4W_9: .equ h'000a0000 ; Area 4 has 9 wait states
BSC_WCR2_A4W_12: .equ h'000c0000 ; Area 4 has 12 wait states
BSC_WCR2_A4W_15: .equ h'000e0000 ; Area 4 has 15 wait states
; When Normal Memory is Used
BSC_WCR2_A3W_NORMAL: .equ h'0000e000 ; Area 3 wait state mask
BSC_WCR2_A3W_NORMAL_0: .equ h'00000000 ; Area 3 has 0 wait states
BSC_WCR2_A3W_NORMAL_1: .equ h'00002000 ; Area 3 has 1 wait states
BSC_WCR2_A3W_NORMAL_2: .equ h'00004000 ; Area 3 has 2 wait states
BSC_WCR2_A3W_NORMAL_3: .equ h'00006000 ; Area 3 has 3 wait states
BSC_WCR2_A3W_NORMAL_6: .equ h'00008000 ; Area 3 has 6 wait states
BSC_WCR2_A3W_NORMAL_9: .equ h'0000a000 ; Area 3 has 9 wait states
BSC_WCR2_A3W_NORMAL_12: .equ h'0000c000 ; Area 3 has 12 wait states
BSC_WCR2_A3W_NORMAL_15: .equ h'0000e000 ; Area 3 has 15 wait states
; When DRAM, Synchronours DRAM is Used
BSC_WCR2_A3W_DRAM: .equ h'0000e000 ; Area 3 assertion width mask
BSC_WCR2_A3W_DRAM_1: .equ h'00000000 ; Area 3 has 1 assertion width
BSC_WCR2_A3W_DRAM_2: .equ h'00002000 ; Area 3 has 2 assertion width
BSC_WCR2_A3W_DRAM_3: .equ h'00004000 ; Area 3 has 3 assertion width
BSC_WCR2_A3W_DRAM_4: .equ h'00006000 ; Area 3 has 4 assertion width
BSC_WCR2_A3W_DRAM_7: .equ h'00008000 ; Area 3 has 7 assertion width
BSC_WCR2_A3W_DRAM_10: .equ h'0000a000 ; Area 3 has 10 assertion width
BSC_WCR2_A3W_DRAM_13: .equ h'0000c000 ; Area 3 has 13 assertion width
BSC_WCR2_A3W_DRAM_16: .equ h'0000e000 ; Area 3 has 16 assertion width
; When Normal Memory is Used
BSC_WCR2_A2W_NORMAL: .equ h'00000e00 ; Area 2 wait state mask
BSC_WCR2_A2W_NORMAL_0: .equ h'00000000 ; Area 2 has 0 wait states
BSC_WCR2_A2W_NORMAL_1: .equ h'00000200 ; Area 2 has 1 wait states
BSC_WCR2_A2W_NORMAL_2: .equ h'00000400 ; Area 2 has 2 wait states
BSC_WCR2_A2W_NORMAL_3: .equ h'00000600 ; Area 2 has 3 wait states
BSC_WCR2_A2W_NORMAL_6: .equ h'00000800 ; Area 2 has 6 wait states
BSC_WCR2_A2W_NORMAL_9: .equ h'00000a00 ; Area 2 has 9 wait states
BSC_WCR2_A2W_NORMAL_12: .equ h'00000c00 ; Area 2 has 12 wait states
BSC_WCR2_A2W_NORMAL_15: .equ h'00000e00 ; Area 2 has 15 wait states
; When DRAM, Synchronours DRAM is Used
BSC_WCR2_A2W_DRAM: .equ h'00000e00 ; Area 2 assertion width mask
BSC_WCR2_A2W_DRAM_1: .equ h'00000000 ; Area 2 has 1 assertion width
BSC_WCR2_A2W_DRAM_2: .equ h'00000200 ; Area 2 has 2 assertion width
BSC_WCR2_A2W_DRAM_3: .equ h'00000400 ; Area 2 has 3 assertion width
BSC_WCR2_A2W_DRAM_4: .equ h'00000600 ; Area 2 has 4 assertion width
BSC_WCR2_A2W_DRAM_7: .equ h'00000800 ; Area 2 has 7 assertion width
BSC_WCR2_A2W_DRAM_10: .equ h'00000a00 ; Area 2 has 10 assertion width
BSC_WCR2_A2W_DRAM_13: .equ h'00000c00 ; Area 2 has 13 assertion width
BSC_WCR2_A2W_DRAM_16: .equ h'00000e00 ; Area 2 has 16 assertion width
BSC_WCR2_A1W: .equ h'000001c0 ; Area 1 wait state mask
BSC_WCR2_A1W_0: .equ h'00000000 ; Area 1 has 0 wait states
BSC_WCR2_A1W_1: .equ h'00000040 ; Area 1 has 1 wait states
BSC_WCR2_A1W_2: .equ h'00000080 ; Area 1 has 2 wait states
BSC_WCR2_A1W_3: .equ h'000000c0 ; Area 1 has 3 wait states
BSC_WCR2_A1W_6: .equ h'00000100 ; Area 1 has 6 wait states
BSC_WCR2_A1W_9: .equ h'00000140 ; Area 1 has 9 wait states
BSC_WCR2_A1W_12: .equ h'00000180 ; Area 1 has 12 wait states
BSC_WCR2_A1W_15: .equ h'000001c0 ; Area 1 has 15 wait states
BSC_WCR2_A0W: .equ h'00000038 ; Area 0 wait state mask
BSC_WCR2_A0W_0: .equ h'00000000 ; Area 0 has 0 wait states
BSC_WCR2_A0W_1: .equ h'00000008 ; Area 0 has 1 wait states
BSC_WCR2_A0W_2: .equ h'00000010 ; Area 0 has 2 wait states
BSC_WCR2_A0W_3: .equ h'00000018 ; Area 0 has 3 wait states
BSC_WCR2_A0W_6: .equ h'00000020 ; Area 0 has 3 wait states
BSC_WCR2_A0W_9: .equ h'00000028 ; Area 0 has 3 wait states
BSC_WCR2_A0W_12: .equ h'00000030 ; Area 0 has 3 wait states
BSC_WCR2_A0W_15: .equ h'00000038 ; Area 0 has 3 wait states
BSC_WCR2_A0B: .equ h'00000007 ; Area 0 wait state mask
BSC_WCR2_A0B_0: .equ h'00000000 ; Area 0 has 0 wait states
BSC_WCR2_A0B_1: .equ h'00000001 ; Area 0 has 1 wait states
BSC_WCR2_A0B_2: .equ h'00000002 ; Area 0 has 2 wait states
BSC_WCR2_A0B_3: .equ h'00000003 ; Area 0 has 3 wait states
BSC_WCR2_A0B_4: .equ h'00000004 ; Area 0 has 4 wait states
BSC_WCR2_A0B_5: .equ h'00000005 ; Area 0 has 5 wait states
BSC_WCR2_A0B_6: .equ h'00000006 ; Area 0 has 6 wait states
BSC_WCR2_A0B_7: .equ h'00000007 ; Area 0 has 7 wait states
; WCR3 Wait state control register 3 fields.
BSC_WCR3_A6S: .equ h'04000000 ; Area 6 write strobe setup time mask
BSC_WCR3_A6S_0: .equ h'00000000 ; Area 6 has 0 wait inserted in setup
BSC_WCR3_A6S_1: .equ h'04000000 ; Area 6 has 1 wait inserted in setup
BSC_WCR3_A6H: .equ h'03000000 ; Area 6 data hold time mask
BSC_WCR3_A6H_0: .equ h'00000000 ; Area 6 has 0 wait inserted in hold
BSC_WCR3_A6H_1: .equ h'01000000 ; Area 6 has 1 wait inserted in hold
BSC_WCR3_A6H_2: .equ h'02000000 ; Area 6 has 2 wait inserted in hold
BSC_WCR3_A6H_3: .equ h'03000000 ; Area 6 has 3 wait inserted in hold
BSC_WCR3_A5S: .equ h'00400000 ; Area 5 write strobe setup time mask
BSC_WCR3_A5S_0: .equ h'00000000 ; Area 5 has 0 wait inserted in setup
BSC_WCR3_A5S_1: .equ h'00400000 ; Area 5 has 1 wait inserted in setup
BSC_WCR3_A5H: .equ h'00300000 ; Area 5 data hold time mask
BSC_WCR3_A5H_0: .equ h'00000000 ; Area 5 has 0 wait inserted in hold
BSC_WCR3_A5H_1: .equ h'00100000 ; Area 5 has 1 wait inserted in hold
BSC_WCR3_A5H_2: .equ h'00200000 ; Area 5 has 2 wait inserted in hold
BSC_WCR3_A5H_3: .equ h'00300000 ; Area 5 has 3 wait inserted in hold
BSC_WCR3_A4S: .equ h'00040000 ; Area 4 write strobe setup time mask
BSC_WCR3_A4S_0: .equ h'00000000 ; Area 4 has 0 wait inserted in setup
BSC_WCR3_A4S_1: .equ h'00040000 ; Area 4 has 1 wait inserted in setup
BSC_WCR3_A4H: .equ h'00030000 ; Area 4 data hold time mask
BSC_WCR3_A4H_0: .equ h'00000000 ; Area 4 has 0 wait inserted in hold
BSC_WCR3_A4H_1: .equ h'00010000 ; Area 4 has 1 wait inserted in hold
BSC_WCR3_A4H_2: .equ h'00020000 ; Area 4 has 2 wait inserted in hold
BSC_WCR3_A4H_3: .equ h'00030000 ; Area 4 has 3 wait inserted in hold
BSC_WCR3_A3S: .equ h'00004000 ; Area 3 write strobe setup time mask
BSC_WCR3_A3S_0: .equ h'00000000 ; Area 3 has 0 wait inserted in setup
BSC_WCR3_A3S_1: .equ h'00004000 ; Area 3 has 1 wait inserted in setup
BSC_WCR3_A3H: .equ h'00003000 ; Area 3 data hold time mask
BSC_WCR3_A3H_0: .equ h'00000000 ; Area 3 has 0 wait inserted in hold
BSC_WCR3_A3H_1: .equ h'00001000 ; Area 3 has 1 wait inserted in hold
BSC_WCR3_A3H_2: .equ h'00002000 ; Area 3 has 2 wait inserted in hold
BSC_WCR3_A3H_3: .equ h'00003000 ; Area 3 has 3 wait inserted in hold
BSC_WCR3_A2S: .equ h'00000400 ; Area 2 write strobe setup time mask
BSC_WCR3_A2S_0: .equ h'00000000 ; Area 2 has 0 wait inserted in setup
BSC_WCR3_A2S_1: .equ h'00000400 ; Area 2 has 1 wait inserted in setup
BSC_WCR3_A2H: .equ h'00000300 ; Area 2 data hold time mask
BSC_WCR3_A2H_0: .equ h'00000000 ; Area 2 has 0 wait inserted in hold
BSC_WCR3_A2H_1: .equ h'00000100 ; Area 2 has 1 wait inserted in hold
BSC_WCR3_A2H_2: .equ h'00000200 ; Area 2 has 2 wait inserted in hold
BSC_WCR3_A2H_3: .equ h'00000300 ; Area 2 has 3 wait inserted in hold
BSC_WCR3_A1S: .equ h'00000040 ; Area 1 write strobe setup time mask
BSC_WCR3_A1S_0: .equ h'00000000 ; Area 1 has 0 wait inserted in setup
BSC_WCR3_A1S_1: .equ h'00000040 ; Area 1 has 1 wait inserted in setup
BSC_WCR3_A1H: .equ h'00000030 ; Area 1 data hold time mask
BSC_WCR3_A1H_0: .equ h'00000000 ; Area 1 has 0 wait inserted in hold
BSC_WCR3_A1H_1: .equ h'00000010 ; Area 1 has 1 wait inserted in hold
BSC_WCR3_A1H_2: .equ h'00000020 ; Area 1 has 2 wait inserted in hold
BSC_WCR3_A1H_3: .equ h'00000030 ; Area 1 has 3 wait inserted in hold
BSC_WCR3_A0S: .equ h'00000004 ; Area 0 write strobe setup time mask
BSC_WCR3_A0S_0: .equ h'00000000 ; Area 0 has 0 wait inserted in setup
BSC_WCR3_A0S_1: .equ h'00000004 ; Area 0 has 1 wait inserted in setup
BSC_WCR3_A0H: .equ h'00000003 ; Area 0 data hold time mask
BSC_WCR3_A0H_0: .equ h'00000000 ; Area 0 has 0 wait inserted in hold
BSC_WCR3_A0H_1: .equ h'00000001 ; Area 0 has 1 wait inserted in hold
BSC_WCR3_A0H_2: .equ h'00000002 ; Area 0 has 2 wait inserted in hold
BSC_WCR3_A0H_3: .equ h'00000003 ; Area 0 has 3 wait inserted in hold
; MCR Individual memory control register (RAS/CAS timing and burst control for
; DRAM, SRAM and PSRAM, address multiplexing, and refresh control.
BSC_MCR_RASD: .equ h'80000000 ; RAS down mode
BSC_MCR_MRSET: .equ h'40000000 ; Mode register set
BSC_MCR_TRC: .equ h'38000000 ; RAS precharge time mask
BSC_MCR_TRC_0: .equ h'00000000 ; 0 cycle
BSC_MCR_TRC_3: .equ h'08000000 ; 3 cycle
BSC_MCR_TRC_6: .equ h'10000000 ; 6 cycles
BSC_MCR_TRC_9: .equ h'18000000 ; 9 cycles
BSC_MCR_TRC_12: .equ h'20000000 ; 12 cycles
BSC_MCR_TRC_15: .equ h'28000000 ; 15 cycles
BSC_MCR_TRC_18: .equ h'30000000 ; 18 cycles
BSC_MCR_TRC_21: .equ h'38000000 ; 21 cycles
BSC_MCR_TCAS: .equ h'00800000 ; CAS Assertion Period 0:1, 1:2
BSC_MCR_TPC: .equ h'00380000 ; RAS precharge time mask
BSC_MCR_TPC_0: .equ h'00000000 ; 0 cycle
BSC_MCR_TPC_1: .equ h'00080000 ; 1 cycles
BSC_MCR_TPC_2: .equ h'00100000 ; 2 cycles
BSC_MCR_TPC_3: .equ h'00180000 ; 3 cycles
BSC_MCR_TPC_4: .equ h'00200000 ; 4 cycles
BSC_MCR_TPC_5: .equ h'00280000 ; 5 cycles
BSC_MCR_TPC_6: .equ h'00300000 ; 6 cycles
BSC_MCR_TPC_7: .equ h'00380000 ; 7 cycles
BSC_MCR_RCD: .equ h'00030000 ; RAS-CAS delay mask
BSC_MCR_RCD_2: .equ h'00000000 ; 2 cycles
BSC_MCR_RCD_3: .equ h'00010000 ; 3 cycles
BSC_MCR_RCD_4: .equ h'00020000 ; 4 cycles
BSC_MCR_RCD_5: .equ h'00030000 ; 5 cycles
BSC_MCR_TRWL: .equ h'0000e000 ; Write-precharge delay
BSC_MCR_TRWL_1: .equ h'00000000 ; 1 cycle
BSC_MCR_TRWL_2: .equ h'00002000 ; 2 cycles
BSC_MCR_TRWL_3: .equ h'00004000 ; 3 cycles
BSC_MCR_TRWL_4: .equ h'00006000 ; 4 cycles
BSC_MCR_TRWL_5: .equ h'00008000 ; 5 cycles
BSC_MCR_TRAS: .equ h'00001c00 ; RAS assertion period mask
BSC_MCR_TRAS_2: .equ h'00000000 ; 2 cycles
BSC_MCR_TRAS_3: .equ h'00000400 ; 3 cycles
BSC_MCR_TRAS_4: .equ h'00000800 ; 4 cycles
BSC_MCR_TRAS_5: .equ h'00000c00 ; 5 cycles
BSC_MCR_TRAS_6: .equ h'00001000 ; 6 cycles
BSC_MCR_TRAS_7: .equ h'00001400 ; 7 cycles
BSC_MCR_TRAS_8: .equ h'00001800 ; 8 cycles
BSC_MCR_TRAS_9: .equ h'00001c00 ; 9 cycles
BSC_MCR_BE: .equ h'00000200 ; Burst enable
BSC_MCR_SZ: .equ h'00000180 ; Memory data size mask
BSC_MCR_SZ_64: .equ h'00000000 ; Memory data size 64
BSC_MCR_SZ_16: .equ h'00000100 ; Memory data size 16
BSC_MCR_SZ_32: .equ h'00000180 ; Memory data size 32
BSC_MCR_AMXEXT: .equ h'00000040 ; Address multiplexing
BSC_MCR_AMX: .equ h'00000038 ; Address multiplex mask
BSC_MCR_AMX_8: .equ h'00000000 ; 8-bit column address product
BSC_MCR_AMX_9: .equ h'00000008 ; 9-bit column address product
BSC_MCR_AMX_10: .equ h'00000010 ; 10-bit column address product
BSC_MCR_AMX_11: .equ h'00000018 ; 11-bit column address product
BSC_MCR_AMX_12: .equ h'00000020 ; 12-bit column address product
BSC_MCR_RFSH: .equ h'00000004 ; Refresh enable
BSC_MCR_RMODE: .equ h'00000002 ; Refresh mode, 0 => ordinary, 1 => self
BSC_MCR_EDOMODE: .equ h'00000001 ; EDO mode 1:EDO, 0:SDRAM or SGRAM
; PCMCIA Control Register(PCR)
BSC_PCR_A5PCW: .equ h'c000 ; PCMCIA area 5 wait mask
BSC_PCR_A5PCW_0: .equ h'0000 ; Area 5 has 0 wait inserted
BSC_PCR_A5PCW_15: .equ h'4000 ; Area 5 has 15 wait inserted
BSC_PCR_A5PCW_30: .equ h'8000 ; Area 5 has 30 wait inserted
BSC_PCR_A5PCW_50: .equ h'c000 ; Area 5 has 50 wait inserted
BSC_PCR_A6PCW: .equ h'3000 ; PCMCIA area 6 wait mask
BSC_PCR_A6PCW_0: .equ h'0000 ; Area 6 has 0 wait inserted
BSC_PCR_A6PCW_15: .equ h'1000 ; Area 6 has 15 wait inserted
BSC_PCR_A6PCW_30: .equ h'2000 ; Area 6 has 30 wait inserted
BSC_PCR_A6PCW_50: .equ h'3000 ; Area 6 has 50 wait inserted
BSC_PCR_A5TED: .equ h'0e00 ; PCMCIA area 5 address assertion delay mask
BSC_PCR_A5TED_0: .equ h'0000 ; Area 5 has 0 wait inserted
BSC_PCR_A5TED_1: .equ h'0200 ; Area 5 has 1 wait inserted
BSC_PCR_A5TED_2: .equ h'0400 ; Area 5 has 2 wait inserted
BSC_PCR_A5TED_3: .equ h'0600 ; Area 5 has 3 wait inserted
BSC_PCR_A5TED_6: .equ h'0800 ; Area 5 has 6 wait inserted
BSC_PCR_A5TED_9: .equ h'0a00 ; Area 5 has 9 wait inserted
BSC_PCR_A5TED_12: .equ h'0c00 ; Area 5 has 12 wait inserted
BSC_PCR_A5TED_15: .equ h'0e00 ; Area 5 has 15 wait inserted
BSC_PCR_A6TED: .equ h'01c0 ; PCMCIA area 6 address assertion delay mask
BSC_PCR_A6TED_0: .equ h'0000 ; Area 6 has 0 wait inserted
BSC_PCR_A6TED_1: .equ h'0040 ; Area 6 has 1 wait inserted
BSC_PCR_A6TED_2: .equ h'0080 ; Area 6 has 2 wait inserted
BSC_PCR_A6TED_3: .equ h'00c0 ; Area 6 has 3 wait inserted
BSC_PCR_A6TED_6: .equ h'0100 ; Area 6 has 6 wait inserted
BSC_PCR_A6TED_9: .equ h'0140 ; Area 6 has 9 wait inserted
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