sh4.inc

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· INC 代码 · 共 1,099 行 · 第 1/4 页

CPG_WTCSR_COOKIE:			.equ	h'a500	; OR with new value before writing
CPG_WTCSR_TME:				.equ	h'0080	; Timer enable
CPG_WTCSR_WT:				.equ	h'0040	; Timer mode select, 1 <=> watchdog
CPG_WTCSR_RSTS:				.equ	h'0020	; Reset select
CPG_WTCSR_WOVF:				.equ	h'0010	; Watchdog timer overflow
CPG_WTCSR_IOVF:				.equ	h'0008	; Interval timer overflow

CPG_WTCSR_CKS:				.equ	h'0007	; Clock select, periph clock div ratio
CPG_WTCSR_CKS_32:			.equ	h'0000	; /32
CPG_WTCSR_CKS_64:			.equ	h'0001	; /64
CPG_WTCSR_CKS_128:			.equ	h'0002	; /128
CPG_WTCSR_CKS_256:			.equ	h'0003	; /256
CPG_WTCSR_CKS_512:			.equ	h'0004	; /512
CPG_WTCSR_CKS_1024:			.equ	h'0005	; /1024
CPG_WTCSR_CKS_2048:			.equ	h'0006	; /2048
CPG_WTCSR_CKS_4096:			.equ	h'0007	; /4096

; Stanby control register 2

CPG_STBCR2_DSLP:			.equ	h'80	; Deep sleep mode

;
; Real Time Clock control registers 
;

RTC_REGBASE					.equ	h'FFC80000
RTC_REGSIZE					.equ	h'0040

RTC_R64CNT_OFFSET			.equ	h'0000
RTC_RSECCNT_OFFSET			.equ	h'0004
RTC_RMINCNT_OFFSET			.equ	h'0008
RTC_RHRCNT_OFFSET			.equ	h'000C
RTC_RWKCNT_OFFSET			.equ	h'0010
RTC_RDAYCNT_OFFSET			.equ	h'0014
RTC_RMONCNT_OFFSET			.equ	h'0018
RTC_RYRCNT_OFFSET			.equ	h'001C
RTC_RSECAR_OFFSET			.equ	h'0020
RTC_RMINAR_OFFSET			.equ	h'0024
RTC_RHRAR_OFFSET			.equ	h'0028
RTC_RWKAR_OFFSET			.equ	h'002C
RTC_RDAYAR_OFFSET			.equ	h'0030
RTC_RMONAR_OFFSET			.equ	h'0034
RTC_RCR1_OFFSET				.equ	h'0038
RTC_RCR2_OFFSET				.equ	h'003c

RTC_R64CNT					.equ	RTC_REGBASE + RTC_R64CNT_OFFSET
RTC_RSECCNT					.equ	RTC_REGBASE + RTC_RSECCNT_OFFSET
RTC_RMINCNT					.equ	RTC_REGBASE + RTC_RMINCNT_OFFSET
RTC_RHRCNT					.equ	RTC_REGBASE + RTC_RHRCNT_OFFSET
RTC_RWKCNT					.equ	RTC_REGBASE + RTC_RWKCNT_OFFSET
RTC_RDAYCNT					.equ	RTC_REGBASE + RTC_RDAYCNT_OFFSET
RTC_RMONCNT					.equ	RTC_REGBASE + RTC_RMONCNT_OFFSET
RTC_RYRCNT					.equ	RTC_REGBASE + RTC_RYRCNT_OFFSET
RTC_RSECAR					.equ	RTC_REGBASE + RTC_RSECAR_OFFSET
RTC_RMINAR					.equ	RTC_REGBASE + RTC_RMINAR_OFFSET
RTC_RHRAR					.equ	RTC_REGBASE + RTC_RHRAR_OFFSET
RTC_RWKAR					.equ	RTC_REGBASE + RTC_RWKAR_OFFSET
RTC_RDAYAR					.equ	RTC_REGBASE + RTC_RDAYAR_OFFSET
RTC_RMONAR					.equ	RTC_REGBASE + RTC_RMONAR_OFFSET
RTC_RCR1					.equ	RTC_REGBASE + RTC_RCR1_OFFSET
RTC_RCR2					.equ	RTC_REGBASE + RTC_RCR2_OFFSET

; Second Alarm Register (RSECAR)

RTC_RSECAR_ENB				.equ	h'80

; Minute Alarm Register (RMINAR)

RTC_RMINAR_ENB				.equ	h'80

; Hour Alarm Register (RHRAR)

RTC_RHRAR_ENB				.equ	h'80

; Day of Week Alarm Register (RWKAR)

RTC_RWKAR_ENB				.equ	h'80

; Day Alarm Register (RDAYAR)

RTC_RDAYAR_ENB				.equ	h'80

; Month Alarm Register (RMONAR)

RTC_RMONAR_ENB				.equ	h'80

; RTC Control Register1 (RCR1)

RTC_RCR1_CF					.equ	h'80
RTC_RCR1_CIE				.equ	h'10
RTC_RCR1_AIE				.equ	h'08
RTC_RCR1_AF					.equ	h'01

; RTC Control Register2 (RCR2)

RTC_RCR2_PEF				.equ	h'80
RTC_RCR2_RES_2				.equ	h'70	;Periodic interrupt generated every 2 second  
RTC_RCR2_RES_1				.equ	h'60	;Periodic interrupt generated every 1 second  
RTC_RCR2_RES_1_2			.equ	h'50	;Periodic interrupt generated every 1/2 second  
RTC_RCR2_RES_1_4			.equ	h'40	;Periodic interrupt generated every 1/4 second  
RTC_RCR2_RES_1_16			.equ	h'30	;Periodic interrupt generated every 1/16 second  
RTC_RCR2_RES_1_64			.equ	h'20	;Periodic interrupt generated every 1/64 second  
RTC_RCR2_RES_1_256			.equ	h'10	;Periodic interrupt generated every 1/256 second  
RTC_RCR2_RES_NO_PINT		.equ	h'00	;NO periodic interrupt generation
RTC_RCR2_RTCEN				.equ	h'08
RTC_RCR2_ADJ				.equ	h'04
RTC_RCR2_RESET				.equ	h'02
RTC_RCR2_START				.equ	h'01

;
; Interrupt Controller registers
;

INTC_REGBASE				.equ	h'FFD00000
INTC_REGSIZE				.equ	h'0020

INTC_ICR_OFFSET				.equ	h'0000	; intr controll reg offset
INTC_IPRA_OFFSET			.equ	h'0004	; intr priority level A  offset
INTC_IPRB_OFFSET			.equ	h'0008	; intr priority level B  offset
INTC_IPRC_OFFSET			.equ	h'000C	; intr priority level C  offset

INTC_ICR					.equ	(INTC_REGBASE + INTC_ICR_OFFSET)
INTC_IPRA					.equ	(INTC_REGBASE + INTC_IPRA_OFFSET)
INTC_IPRB					.equ	(INTC_REGBASE + INTC_IPRB_OFFSET)
INTC_IPRC					.equ	(INTC_REGBASE + INTC_IPRC_OFFSET)

; Interrupt Control Register

INTC_ICR_IRL_MASK			.equ	h'FF7F
INTC_ICR_IRL_ENCODE			.equ	h'0000
INTC_ICR_IRL_INDEPENDENT	.equ	h'0080

; Interrupt Priority level setting Register A
 
INTC_IPRA_TMU0_MASK			.equ	h'0FFF
INTC_IPRA_TMU1_MASK			.equ	h'F0FF
INTC_IPRA_TMU2_MASK			.equ	h'FF0F
INTC_IPRA_RTC_MASK			.equ	h'FFF0

; Interrupt Priority level setting Register B
 
INTC_IPRB_WDT_MASK			.equ	h'0FFF
INTC_IPRB_REF_MASK			.equ	h'F0FF
INTC_IPRB_SCI_MASK			.equ	h'FF0F

; Interrupt Priority level setting Register C
 
INTC_IPRC_DMAC_MASK			.equ	h'F0FF
INTC_IPRC_SCIF_MASK			.equ	h'FF0F
INTC_IPRC_JTAG_MASK			.equ	h'FFF0

;
; Timer Unit registers
;

TMU_REGBASE					.equ	h'FFD80000
TMU_REGSIZE					.equ	h'0040

TMU_TOCR_OFFSET				.equ	h'0000				;common
TMU_TSTR_OFFSET				.equ	h'0004

TMU_TCOR0_OFFSET			.equ	h'0008				;TMU0
TMU_TCNT0_OFFSET			.equ	h'000C
TMU_TCR0_OFFSET				.equ	h'0010

TMU_TCOR1_OFFSET			.equ	h'0014				;TMU1
TMU_TCNT1_OFFSET			.equ	h'0018
TMU_TCR1_OFFSET				.equ	h'001C

TMU_TCOR2_OFFSET			.equ	h'0020				;TMU2
TMU_TCNT2_OFFSET			.equ	h'0024
TMU_TCR2_OFFSET				.equ	h'0028

TMU_TCPR2_OFFSET			.equ	h'002C

TMU_TOCR					.equ	(TMU_REGBASE + TMU_TOCR_OFFSET)
TMU_TSTR					.equ	(TMU_REGBASE + TMU_TSTR_OFFSET)

TMU_TCOR0					.equ	(TMU_REGBASE + TMU_TCOR0_OFFSET)
TMU_TCNT0					.equ	(TMU_REGBASE + TMU_TCNT0_OFFSET)
TMU_TCR0					.equ	(TMU_REGBASE + TMU_TCR0_OFFSET)

TMU_TCOR1					.equ	(TMU_REGBASE + TMU_TCOR1_OFFSET)
TMU_TCNT1					.equ	(TMU_REGBASE + TMU_TCNT1_OFFSET)
TMU_TCR1					.equ	(TMU_REGBASE + TMU_TCR1_OFFSET)

TMU_TCOR2					.equ	(TMU_REGBASE + TMU_TCOR2_OFFSET)
TMU_TCNT2					.equ	(TMU_REGBASE + TMU_TCNT2_OFFSET)
TMU_TCR2					.equ	(TMU_REGBASE + TMU_TCR2_OFFSET)

TMU_TCPR2					.equ	(TMU_REGBASE + TMU_TCPR2_OFFSET)

; Timer Start Register

TMU_TSTR_STR0				.equ	h'01
TMU_TSTR_STR1				.equ	h'02
TMU_TSTR_STR2				.equ	h'04

; Timer Control Register

TMU_TCR_UNF					.equ	h'100	; counter underflowed
TMU_TCR_UNIE				.equ	h'20	; underflow interrupt enable

TMU_TCR_RISE				.equ	h'00	; count on rising edge of clock
TMU_TCR_FALL				.equ	h'08	; count on falling edge of clock
TMU_TCR_BOTH				.equ	h'10	; count on both edges of clock

TMU_TCR_D4					.equ	h'00	; PERIPHERAL clock / 4
TMU_TCR_D16					.equ	h'01	; PERIPHERAL clock / 16
TMU_TCR_D64					.equ	h'02	; PERIPHERAL clock / 64
TMU_TCR_D256				.equ	h'03	; PERIPHERAL clock / 256
TMU_TCR_D1024				.equ	h'04	; PERIPHERAL clock / 1024
TMU_TCR_RTC					.equ	h'06	; real time clock output (16 kHz)
TMU_TCR_EXT					.equ	h'07	; external clock input

;
; Serial Communication Interface (SCI) 
;

SCI_REGBASE					.equ	h'FFE00000	; SH-4 control regs 
SCI_REGSIZE					.equ	h'0020	

SCI_SCSMR1_OFFSET			.equ	h'0000		; Serial Mode Register 
SCI_SCBRR1_OFFSET			.equ	h'0004		; Bit rate register 
SCI_SCSCR1_OFFSET			.equ	h'0008		; Serial Control Register 
SCI_SCTDR1_OFFSET			.equ	h'000c		; transmit data register 
SCI_SCSSR1_OFFSET			.equ	h'0010		; Serail Status Register 
SCI_SCRDR1_OFFSET			.equ	h'0014		; Receive Data register 
SCI_SCSPTR1_OFFSET			.equ	h'001c		; Serial Port register 

SCI_SCSMR1					.equ	(SCI_REGBASE + SCI_SCSMR1_OFFSET)
SCI_SCBRR1					.equ	(SCI_REGBASE + SCI_SCBRR1_OFFSET)
SCI_SCSCR1					.equ	(SCI_REGBASE + SCI_SCSCR1_OFFSET)
SCI_SCTDR1					.equ	(SCI_REGBASE + SCI_SCTDR1_OFFSET)
SCI_SCSSR1					.equ	(SCI_REGBASE + SCI_SCSSR1_OFFSET)
SCI_SCRDR1					.equ	(SCI_REGBASE + SCI_SCRDR1_OFFSET)
SCI_SCSPTR1					.equ	(SCI_REGBASE + SCI_SCSPTR1_OFFSET)

;
; Serial Communication Interface with FIFO (SCIF) 
;

SCIF_REGBASE				.equ	h'FFE80000	; SH-4 control regs 
SCIF_REGSIZE				.equ	h'0028	

SCIF_SCSMR2_OFFSET			.equ	h'0000		; Serial Mode Register 
SCIF_SCBRR2_OFFSET			.equ	h'0004		; Bit rate register 
SCIF_SCSCR2_OFFSET			.equ	h'0008		; Serial Control Register 
SCIF_SCFTDR2_OFFSET			.equ	h'000c		; transmit FIFO data register 
SCIF_SCFSR2_OFFSET			.equ	h'0010		; Serail Status Register 
SCIF_SCFRDR2_OFFSET			.equ	h'0014		; Receive Data FIFO register 
SCIF_SCFCR2_OFFSET			.equ	h'0018		; FIFO Control Register 
SCIF_SCFDR2_OFFSET			.equ	h'001c		; FIFO Data Count set register 
SCIF_SCSPTR2_OFFSET			.equ	h'0020		; FIFO Data Count set register 
SCIF_SCLSR2_OFFSET			.equ	h'0024		; FIFO Data Count set register 

SCIF_SCSMR2					.equ	(SCIF_REGBASE + SCIF_SCSMR2_OFFSET)
SCIF_SCBRR2					.equ	(SCIF_REGBASE + SCIF_SCBRR2_OFFSET)
SCIF_SCSCR2					.equ	(SCIF_REGBASE + SCIF_SCSCR2_OFFSET)
SCIF_SCFTDR2				.equ	(SCIF_REGBASE + SCIF_SCFTDR2_OFFSET)
SCIF_SCFSR2					.equ	(SCIF_REGBASE + SCIF_SCFSR2_OFFSET)
SCIF_SCFRDR2				.equ	(SCIF_REGBASE + SCIF_SCFRDR2_OFFSET)
SCIF_SCFCR2					.equ	(SCIF_REGBASE + SCIF_SCFCR2_OFFSET)
SCIF_SCFDR2					.equ	(SCIF_REGBASE + SCIF_SCFDR2_OFFSET)
SCIF_SCSPTR2				.equ	(SCIF_REGBASE + SCIF_SCSPTR2_OFFSET)
SCIF_SCLSR2					.equ	(SCIF_REGBASE + SCIF_SCLSR2_OFFSET)

;
; The SR reg, puts us in priviledged mode, and blocks all interrupts
;

TM_SR						.equ	h'70000000