sh4.h
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 1,105 行 · 第 1/4 页
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/*
Copyright(c) 1998,1999 SIC/Hitachi,Ltd.
Module Name:
sh4.h
Revision History:
26th April 1999 Released
*/
#ifndef SH4_H
#define SH4_H
//
// CCN.
//
#define CCN_REGBASE 0xFF000000 // CCN Register Base Address
#define CCN_REGSIZE 0x40
#define CCN_CCR_OFFSET 0x001C // Cache Control Register Offset
#define CCN_QACR0_OFFSET 0x0038 // Queue Address Control Register 0
#define CCN_QACR1_OFFSET 0x003C // Queue Address Control Register 1
#define CCN_CCR (CCN_REGBASE + CCN_CCR_OFFSET) // Cache Control Register
#define CCN_QACR0 (CCN_REGBASE + CCN_QACR0_OFFSET) // Queue Address Control Register 0
#define CCN_QACR1 (CCN_REGBASE + CCN_QACR1_OFFSET) // Queue Address Control Register 1
// Cache Control Register
#define CCN_CCR_IIX 0x00008000 //IC index mode
#define CCN_CCR_ICI 0x00000800 //IC invalidation
#define CCN_CCR_ICE 0x00000100 //IC enable
#define CCN_CCR_OIX 0x00000080 //OC index mode
#define CCN_CCR_ORA 0x00000020 //OC RAM enable
#define CCN_CCR_OCI 0x00000008 //OC invalidation
#define CCN_CCR_CB 0x00000004 //Copy-back enable
#define CCN_CCR_WT 0x00000002 //Write-through enable
#define CCN_CCR_OCE 0x00000001 //OC enable
//
// Bus state controller registers.
//
#define BSC_REGBASE 0xFF800000 // Bus Stage Control Register Base Address
#define BSC_REGSIZE 0x2C // Size of all of the BSC regs
#define BSC_BCR1_OFFSET 0x0000 // Bus Control Register 1 Offset Address
#define BSC_BCR2_OFFSET 0x0004 // Bus Control Register 2 Offset Address
#define BSC_WCR1_OFFSET 0x0008 // Wait state Control Register 1 Offset Address
#define BSC_WCR2_OFFSET 0x000C // Wait state Control Register 2 Offset Address
#define BSC_WCR3_OFFSET 0x0010 // Wait state Control Register 3 Offset Address
#define BSC_MCR_OFFSET 0x0014 // Individual Memory Control Register Offset Address
#define BSC_PCR_OFFSET 0x0018 // PCMCIA Control Register Offset Address
#define BSC_RTCSR_OFFSET 0x001C // Refresh Timer Control/Status Register Offset Address
#define BSC_RTCNT_OFFSET 0x0020 // Refresh Timer Counter Offset Address
#define BSC_RTCOR_OFFSET 0x0024 // Refresh Time Constant Register Offset Address
#define BSC_RFCR_OFFSET 0x0028 // Refresh Count Register Offset Address
#define BSC_BCR1 (BSC_REGBASE + BSC_BCR1_OFFSET) // Bus Control Register 1 Offset Address
#define BSC_BCR2 (BSC_REGBASE + BSC_BCR2_OFFSET) // Bus Control Register 2 Offset Address
#define BSC_WCR1 (BSC_REGBASE + BSC_WCR1_OFFSET) // Wait state Control Register 1 Offset Address
#define BSC_WCR2 (BSC_REGBASE + BSC_WCR2_OFFSET) // Wait state Control Register 2 Offset Address
#define BSC_WCR3 (BSC_REGBASE + BSC_WCR3_OFFSET) // Wait state Control Register 3 Offset Address
#define BSC_MCR (BSC_REGBASE + BSC_MCR_OFFSET) // Individual Memory Control Register Offset Address
#define BSC_PCR (BSC_REGBASE + BSC_PCR_OFFSET) // PCMCIA Control Register Offset Address
#define BSC_RTCSR (BSC_REGBASE + BSC_RTCSR_OFFSET) // Refresh Timer Control/Status Register Offset Address
#define BSC_RTCNT (BSC_REGBASE + BSC_RTCNT_OFFSET) // Refresh Timer Counter Offset Address
#define BSC_RTCOR (BSC_REGBASE + BSC_RTCOR_OFFSET) // Refresh Time Constant Register Offset Address
#define BSC_RFCR (BSC_REGBASE + BSC_RFCR_OFFSET) // Refresh Count Register Offset Address
// BCR1 bus control register 1 fields (function and bus cycle status for each area).
#define BSC_BCR1_ENDIAN 0x80000000 // 1 <=> little endian
#define BSC_BCR1_MASTER 0x40000000 // 0:Master, 1:Slave
#define BSC_BCR1_A0MPX 0x20000000 // 0:SRAM, 1:MPX
#define BSC_BCR1_IPUP 0x02000000 // 0:pulled up, 1:not pulled up
#define BSC_BCR1_OPUP 0x01000000 // 0:pulled up, 1:not pulled up
#define BSC_BCR1_A1MBC 0x00200000 // 0:normal, 1:byte control mode
#define BSC_BCR1_A4MBC 0x00100000 // 0:normal, 1:byte control mode
#define BSC_BCR1_BREQEN 0x00080000 // BREQ Enable Bit
#define BSC_BCR1_PSHR 0x00040000 // Partial-Sharing Bit
#define BSC_BCR1_MEMMPX 0x00020000 // Area 1 to Area 6 MPX Bus Specification
#define BSC_BCR1_HIZMEM 0x00008000 // High-Z Control(HIZMEM)
#define BSC_BCR1_HIZCNT 0x00004000 // High-Z Control(HIZCNT)
#define BSC_BCR1_A0BST 0x00003800 // Area 0 burst mask
#define BSC_BCR1_A0BST_N 0x00000000 // Area 0 ordinary memory
#define BSC_BCR1_A0BST_4 0x00000800 // Area 0 burst (4 consecutive accesses)
#define BSC_BCR1_A0BST_8 0x00001000 // Area 0 burst (8 consecutive accesses)
#define BSC_BCR1_A0BST_16 0x00001800 // Area 0 burst (16 consecutive accesses)
#define BSC_BCR1_A0BST_32 0x00002000 // Area 0 burst (32 consecutive accesses)
#define BSC_BCR1_A5BST 0x00000700 // Area 5 burst mask
#define BSC_BCR1_A5BST_N 0x00000000 // Area 5 ordinary memory
#define BSC_BCR1_A5BST_4 0x00000100 // Area 5 burst (4 consecutive accesses)
#define BSC_BCR1_A5BST_8 0x00000200 // Area 5 burst (8 consecutive accesses)
#define BSC_BCR1_A5BST_16 0x00000300 // Area 5 burst (16 consecutive accesses)
#define BSC_BCR1_A5BST_32 0x00000400 // Area 5 burst (32 consecutive accesses)
#define BSC_BCR1_A6BST 0x000000E0 // Area 6 burst mask
#define BSC_BCR1_A6BST_N 0x00000000 // Area 6 ordinary memory
#define BSC_BCR1_A6BST_4 0x00000020 // Area 6 burst (4 consecutive accesses)
#define BSC_BCR1_A6BST_8 0x00000040 // Area 6 burst (8 consecutive accesses)
#define BSC_BCR1_A6BST_16 0x00000060 // Area 6 burst (16 consecutive accesses)
#define BSC_BCR1_A6BST_32 0x00000080 // Area 6 burst (32 consecutive accesses)
#define BSC_BCR1_DRAM 0x0000001C // Areas 2 & 3 mask
#define BSC_BCR1_DRAM_A2N3N 0x00000000 // Area 2 normal, Area 3 normal
#define BSC_BCR1_DRAM_A2N3P 0x00000004 // Area 2 normal, Area 3 PSRAM
#define BSC_BCR1_DRAM_A2N3S 0x00000008 // Area 2 normal, Area 3 SDRAM
#define BSC_BCR1_DRAM_A2S3S 0x0000000C // Area 2 SDRAM, Area 3 SDRAM
#define BSC_BCR1_DRAM_A2N3D 0x00000010 // Area 2 normal, Area 3 DRAM
#define BSC_BCR1_DRAM_A2D3D 0x00000014 // Area 2 DRAM, Area 3 DRAM
#define BSC_BCR1_A56PCM 0x00000001 // Area 5 & 6 are PCMCIA access
// BCR2 bus control register 2 fields (bus size width of each area).
#define BSC_BCR2_A0SZ 0xC000 // Area 0 mask
#define BSC_BCR2_A0SZ_8 0x4000 // Area 0 is 8-bit memory
#define BSC_BCR2_A0SZ_16 0x8000 // Area 0 is 16-bit memory
#define BSC_BCR2_A0SZ_32 0xc000 // Area 0 is 32-bit memory
#define BSC_BCR2_A0SZ_64 0x0000 // Area 0 is 64-bit memory
#define BSC_BCR2_A6SZ 0x3000 // Area 6 mask
#define BSC_BCR2_A6SZ_8 0x1000 // Area 6 is 8-bit memory
#define BSC_BCR2_A6SZ_16 0x2000 // Area 6 is 16-bit memory
#define BSC_BCR2_A6SZ_32 0x3000 // Area 6 is 32-bit memory
#define BSC_BCR2_A6SZ_64 0x0000 // Area 6 is 64-bit memory
#define BSC_BCR2_A5SZ 0x0C00 // Area 5 mask
#define BSC_BCR2_A5SZ_8 0x0400 // Area 5 is 8-bit memory
#define BSC_BCR2_A5SZ_16 0x0800 // Area 5 is 16-bit memory
#define BSC_BCR2_A5SZ_32 0x0c00 // Area 5 is 32-bit memory
#define BSC_BCR2_A5SZ_64 0x0000 // Area 5 is 64-bit memory
#define BSC_BCR2_A4SZ 0x0300 // Area 4 mask
#define BSC_BCR2_A4SZ_8 0x0100 // Area 4 is 8-bit memory
#define BSC_BCR2_A4SZ_16 0x0200 // Area 4 is 16-bit memory
#define BSC_BCR2_A4SZ_32 0x0300 // Area 4 is 32-bit memory
#define BSC_BCR2_A4SZ_64 0x0000 // Area 4 is 64-bit memory
#define BSC_BCR2_A3SZ 0x00C0 // Area 3 mask
#define BSC_BCR2_A3SZ_8 0x0040 // Area 3 is 8-bit memory
#define BSC_BCR2_A3SZ_16 0x0080 // Area 3 is 16-bit memory
#define BSC_BCR2_A3SZ_32 0x00c0 // Area 3 is 32-bit memory
#define BSC_BCR2_A3SZ_64 0x0000 // Area 3 is 64-bit memory
#define BSC_BCR2_A2SZ 0x0030 // Area 2 mask
#define BSC_BCR2_A2SZ_8 0x0010 // Area 2 is 8-bit memory
#define BSC_BCR2_A2SZ_16 0x0020 // Area 2 is 16-bit memory
#define BSC_BCR2_A2SZ_32 0x0030 // Area 2 is 32-bit memory
#define BSC_BCR2_A2SZ_64 0x0000 // Area 2 is 64-bit memory
#define BSC_BCR2_A1SZ 0x000C // Area 1 mask
#define BSC_BCR2_A1SZ_8 0x0004 // Area 1 is 8-bit memory
#define BSC_BCR2_A1SZ_16 0x0008 // Area 1 is 16-bit memory
#define BSC_BCR2_A1SZ_32 0x000c // Area 1 is 32-bit memory
#define BSC_BCR2_A1SZ_64 0x0000 // Area 1 is 64-bit memory
#define BSC_BCR2_PORTEN 0x0001 // Port enable
// WCR1 Wait state control register 1 fields.
#define BSC_WCR1_DMAIW 0x70000000 // DMA mask
#define BSC_WCR1_DMAIW_0 0x00000000 // DMA has 0 idle states
#define BSC_WCR1_DMAIW_1 0x10000000 // DMA has 1 idle states
#define BSC_WCR1_DMAIW_2 0x20000000 // DMA has 2 idle states
#define BSC_WCR1_DMAIW_3 0x30000000 // DMA has 3 idle states
#define BSC_WCR1_DMAIW_6 0x40000000 // DMA has 6 idle states
#define BSC_WCR1_DMAIW_9 0x50000000 // DMA has 9 idle states
#define BSC_WCR1_DMAIW_12 0x60000000 // DMA has 12 idle states
#define BSC_WCR1_DMAIW_15 0x70000000 // DMA has 15 idle states
#define BSC_WCR1_A6IW 0x07000000 // Area 6 mask
#define BSC_WCR1_A6IW_0 0x00000000 // Area 6 has 0 idle states
#define BSC_WCR1_A6IW_1 0x01000000 // Area 6 has 1 idle states
#define BSC_WCR1_A6IW_2 0x02000000 // Area 6 has 2 idle states
#define BSC_WCR1_A6IW_3 0x03000000 // Area 6 has 3 idle states
#define BSC_WCR1_A6IW_6 0x04000000 // Area 6 has 6 idle states
#define BSC_WCR1_A6IW_9 0x05000000 // Area 6 has 9 idle states
#define BSC_WCR1_A6IW_12 0x06000000 // Area 6 has 12 idle states
#define BSC_WCR1_A6IW_15 0x07000000 // Area 6 has 15 idle states
#define BSC_WCR1_A5IW 0x00700000 // Area 5 mask
#define BSC_WCR1_A5IW_0 0x00000000 // Area 5 has 0 idle states
#define BSC_WCR1_A5IW_1 0x00100000 // Area 5 has 1 idle states
#define BSC_WCR1_A5IW_2 0x00200000 // Area 5 has 2 idle states
#define BSC_WCR1_A5IW_3 0x00300000 // Area 5 has 3 idle states
#define BSC_WCR1_A5IW_6 0x00400000 // Area 5 has 6 idle states
#define BSC_WCR1_A5IW_9 0x00500000 // Area 5 has 9 idle states
#define BSC_WCR1_A5IW_12 0x00600000 // Area 5 has 12 idle states
#define BSC_WCR1_A5IW_15 0x00700000 // Area 5 has 15 idle states
#define BSC_WCR1_A4IW 0x00070000 // Area 4 mask
#define BSC_WCR1_A4IW_0 0x00000000 // Area 4 has 0 idle states
#define BSC_WCR1_A4IW_1 0x00010000 // Area 4 has 1 idle states
#define BSC_WCR1_A4IW_2 0x00020000 // Area 4 has 2 idle states
#define BSC_WCR1_A4IW_3 0x00030000 // Area 4 has 3 idle states
#define BSC_WCR1_A4IW_6 0x00040000 // Area 4 has 6 idle states
#define BSC_WCR1_A4IW_9 0x00050000 // Area 4 has 9 idle states
#define BSC_WCR1_A4IW_12 0x00060000 // Area 4 has 12 idle states
#define BSC_WCR1_A4IW_15 0x00070000 // Area 4 has 15 idle states
#define BSC_WCR1_A3IW 0x00007000 // Area 3 mask
#define BSC_WCR1_A3IW_0 0x00000000 // Area 3 has 0 idle states
#define BSC_WCR1_A3IW_1 0x00001000 // Area 3 has 1 idle states
#define BSC_WCR1_A3IW_2 0x00002000 // Area 3 has 2 idle states
#define BSC_WCR1_A3IW_3 0x00003000 // Area 3 has 3 idle states
#define BSC_WCR1_A3IW_6 0x00004000 // Area 3 has 6 idle states
#define BSC_WCR1_A3IW_9 0x00005000 // Area 3 has 9 idle states
#define BSC_WCR1_A3IW_12 0x00006000 // Area 3 has 12 idle states
#define BSC_WCR1_A3IW_15 0x00007000 // Area 3 has 15 idle states
#define BSC_WCR1_A2IW 0x00000700 // Area 2 mask
#define BSC_WCR1_A2IW_0 0x00000000 // Area 2 has 0 idle states
#define BSC_WCR1_A2IW_1 0x00000100 // Area 2 has 1 idle states
#define BSC_WCR1_A2IW_2 0x00000200 // Area 2 has 2 idle states
#define BSC_WCR1_A2IW_3 0x00000300 // Area 2 has 3 idle states
#define BSC_WCR1_A2IW_6 0x00000400 // Area 2 has 6 idle states
#define BSC_WCR1_A2IW_9 0x00000500 // Area 2 has 9 idle states
#define BSC_WCR1_A2IW_12 0x00000600 // Area 2 has 12 idle states
#define BSC_WCR1_A2IW_15 0x00000700 // Area 2 has 15 idle states
#define BSC_WCR1_A1IW 0x00000070 // Area 1 mask
#define BSC_WCR1_A1IW_0 0x00000000 // Area 1 has 0 idle states
#define BSC_WCR1_A1IW_1 0x00000010 // Area 1 has 1 idle states
#define BSC_WCR1_A1IW_2 0x00000020 // Area 1 has 2 idle states
#define BSC_WCR1_A1IW_3 0x00000030 // Area 1 has 3 idle states
#define BSC_WCR1_A1IW_6 0x00000040 // Area 1 has 6 idle states
#define BSC_WCR1_A1IW_9 0x00000050 // Area 1 has 9 idle states
#define BSC_WCR1_A1IW_12 0x00000060 // Area 1 has 12 idle states
#define BSC_WCR1_A1IW_15 0x00000070 // Area 1 has 15 idle states
#define BSC_WCR1_A0IW 0x00000007 // Area 0 mask
#define BSC_WCR1_A0IW_0 0x00000000 // Area 0 has 0 idle states
#define BSC_WCR1_A0IW_1 0x00000001 // Area 0 has 1 idle states
#define BSC_WCR1_A0IW_2 0x00000002 // Area 0 has 2 idle states
#define BSC_WCR1_A0IW_3 0x00000003 // Area 0 has 3 idle states
#define BSC_WCR1_A0IW_6 0x00000004 // Area 0 has 6 idle states
#define BSC_WCR1_A0IW_9 0x00000005 // Area 0 has 9 idle states
#define BSC_WCR1_A0IW_12 0x00000006 // Area 0 has 12 idle states
#define BSC_WCR1_A0IW_15 0x00000007 // Area 0 has 15 idle states
// WCR2 Wait state control register 2 fields.
#define BSC_WCR2_A6W 0xE0000000 // Area 6 wait state mask
#define BSC_WCR2_A6W_0 0x00000000 // Area 6 has 0 wait states
#define BSC_WCR2_A6W_1 0x20000000 // Area 6 has 1 wait states
#define BSC_WCR2_A6W_2 0x40000000 // Area 6 has 2 wait states
#define BSC_WCR2_A6W_3 0x60000000 // Area 6 has 3 wait states
#define BSC_WCR2_A6W_6 0x80000000 // Area 6 has 6 wait states
#define BSC_WCR2_A6W_9 0xA0000000 // Area 6 has 9 wait states
#define BSC_WCR2_A6W_12 0xC0000000 // Area 6 has 12 wait states
#define BSC_WCR2_A6W_15 0xE0000000 // Area 6 has 15 wait states
#define BSC_WCR2_A6B 0x1C000000 // Area 6 burst sycle mask
#define BSC_WCR2_A6B_0 0x00000000 // Area 6 has 0 states per data transfer
#define BSC_WCR2_A6B_1 0x04000000 // Area 6 has 1 states per data transfer
#define BSC_WCR2_A6B_2 0x08000000 // Area 6 has 2 states per data transfer
#define BSC_WCR2_A6B_3 0x0C000000 // Area 6 has 3 states per data transfer
#define BSC_WCR2_A6B_4 0x10000000 // Area 6 has 4 states per data transfer
#define BSC_WCR2_A6B_5 0x14000000 // Area 6 has 5 states per data transfer
#define BSC_WCR2_A6B_6 0x18000000 // Area 6 has 6 states per data transfer
#define BSC_WCR2_A6B_7 0x1C000000 // Area 6 has 7 states per data transfer
#define BSC_WCR2_A5W 0x03800000 // Area 5 wait state mask
#define BSC_WCR2_A5W_0 0x00000000 // Area 5 has 0 wait states
#define BSC_WCR2_A5W_1 0x00800000 // Area 5 has 1 wait states
#define BSC_WCR2_A5W_2 0x01000000 // Area 5 has 2 wait states
#define BSC_WCR2_A5W_3 0x01800000 // Area 5 has 3 wait states
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