sh4.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 1,105 行 · 第 1/4 页

#define	BSC_PCR_A6TED_12			0x0180	// Area 6 has 12 wait inserted 
#define	BSC_PCR_A6TED_15			0x01C0	// Area 6 has 15 wait inserted 

#define	BSC_PCR_A5TEH				0x0038	// PCMCIA area 5 negation address delay mask 
#define	BSC_PCR_A5TEH_0				0x0000	// Area 5 has 0 wait inserted 
#define	BSC_PCR_A5TEH_1				0x0008	// Area 5 has 1 wait inserted 
#define	BSC_PCR_A5TEH_2				0x0010	// Area 5 has 2 wait inserted 
#define	BSC_PCR_A5TEH_3				0x0018	// Area 5 has 3 wait inserted 
#define	BSC_PCR_A5TEH_6				0x0020	// Area 5 has 6 wait inserted 
#define	BSC_PCR_A5TEH_9				0x0028	// Area 5 has 9 wait inserted 
#define	BSC_PCR_A5TEH_12			0x0030	// Area 5 has 12 wait inserted 
#define	BSC_PCR_A5TEH_15			0x0038	// Area 5 has 15 wait inserted 

#define	BSC_PCR_A6TEH				0x0007	// PCMCIA area 6 negation address delay mask 
#define	BSC_PCR_A6TEH_0				0x0000	// Area 6 has 0 wait inserted 
#define	BSC_PCR_A6TEH_1				0x0001	// Area 6 has 1 wait inserted 
#define	BSC_PCR_A6TEH_2				0x0002	// Area 6 has 2 wait inserted 
#define	BSC_PCR_A6TEH_3				0x0003	// Area 6 has 3 wait inserted 
#define	BSC_PCR_A6TEH_6				0x0004	// Area 6 has 6 wait inserted 
#define	BSC_PCR_A6TEH_9				0x0005	// Area 6 has 9 wait inserted 
#define	BSC_PCR_A6TEH_12			0x0006	// Area 6 has 12 wait inserted 
#define	BSC_PCR_A6TEH_15			0x0007	// Area 6 has 15 wait inserted 

// Synchronous DRAM Mode Register(SDMR)  

// Values that will be written to many of the following registers must be ORed 
// with their corresponding *_*_COOKIE value before writing the register. 
// Otherwise, the hardware will reject (ignore) the write. 

// RTCSR  Refresh timer control/status register (refresh cycle, interrupt enable, 
// and the interrupt's cycle). 

#define BSC_SDMR2_COOKIE			0xFF900000	// OR with new value before writing
#define BSC_SDMR3_COOKIE			0xFF940000	// OR with new value before writing

#define	BSC_SDMR3_190				0x00000190	// 32bit, LMODE=3, WT=0, BL=4, 

#define	BSC_RTCSR_COOKIE			0xA500		// OR with new value before writing 
#define	BSC_RTCSR_CMF				0x0080		// Predicate, RTCNT == RTCOR 
#define	BSC_RTCSR_CMIE				0x0040		// Enable an interrupt via CMF 

#define	BSC_RTCSR_CKS				0x0038		// Clock select mask 
#define	BSC_RTCSR_CKS_DISABLE		0x0000		// Disable clock input 
#define	BSC_RTCSR_CKS_4				0x0008		// CKIO/4 
#define	BSC_RTCSR_CKS_16			0x0010		// CKIO/16 
#define	BSC_RTCSR_CKS_64			0x0018		// CKIO/64 
#define	BSC_RTCSR_CKS_256			0x0020		// CKIO/256 
#define	BSC_RTCSR_CKS_1024			0x0028		// CKIO/1024 
#define	BSC_RTCSR_CKS_2048			0x0030		// CKIO/2048  
#define	BSC_RTCSR_CKS_4096			0x0038		// CKIO/4096 

#define	BSC_RTCSR_OVF				0x0004		// RFCR has exceeded count limit in LMTS 
#define	BSC_RTCSR_OVIE				0x0002		// Enable an interrupt via OVF 
#define	BSC_RTCSR_LMTS				0x0001		// Count limit  0 => 1024, 1 => 512 

// RTCNT  Refresh timer counter. 

#define	BSC_RTCNT_COOKIE			0xA500		// OR with new value before writing 
#define	BSC_RTCNT_COUNT_FF			0x00FF		// Refresh timer counter mask 
#define	BSC_RTCNT_COUNT_00			0x0000		// Refresh timer counter mask 

// RTCOR  Refresh time constant register. 

#define	BSC_RTCOR_COOKIE			0xA500		// OR with new value before writing 
#define	BSC_RTCOR_COUNT				0x00FF		// Refresh time constant mask 

// RFCR  Refresh count register. 

#define	BSC_RFCR_COOKIE				0xA400		// OR with new value before writing 
#define	BSC_RFCR_COUNT				0x03FF		// Refresh count mask 

//
// DMAC registers
//

#define	DMAC_REGBASE				0xFFA00000
#define	DMAC_REGSIZE				0x0044

#define	DMAC_SAR0_OFFSET			0x0000
#define	DMAC_DAR0_OFFSET			0x0004
#define	DMAC_DMATCR0_OFFSET			0x0008
#define	DMAC_CHCR0_OFFSET			0x000C

#define	DMAC_SAR1_OFFSET			0x0010
#define	DMAC_DAR1_OFFSET			0x0014
#define	DMAC_DMATCR1_OFFSET			0x0018
#define	DMAC_CHCR1_OFFSET			0x001C

#define	DMAC_SAR2_OFFSET			0x0020
#define	DMAC_DAR2_OFFSET			0x0024
#define	DMAC_DMATCR2_OFFSET			0x0028
#define	DMAC_CHCR2_OFFSET			0x002C

#define	DMAC_SAR3_OFFSET			0x0030
#define	DMAC_DAR3_OFFSET			0x0034
#define	DMAC_DMATCR3_OFFSET			0x0038
#define	DMAC_CHCR3_OFFSET			0x003C

#define	DMAC_DMAOR_OFFSET			0x0040
					
#define	DMAC_SAR0					(DMAC_REGBASE + DMAC_SAR0_OFFSET)
#define	DMAC_DAR0					(DMAC_REGBASE + DMAC_DAR0_OFFSET)
#define	DMAC_DMATCR0				(DMAC_REGBASE + DMAC_DMATCR0_OFFSET)
#define	DMAC_CHCR0					(DMAC_REGBASE + DMAC_CHCR0_OFFSET)

#define	DMAC_SAR1					(DMAC_REGBASE + DMAC_SAR1_OFFSET)
#define	DMAC_DAR1					(DMAC_REGBASE + DMAC_DAR1_OFFSET)
#define	DMAC_DMATCR1				(DMAC_REGBASE + DMAC_DMATCR1_OFFSET)
#define	DMAC_CHCR1					(DMAC_REGBASE + DMAC_CHCR1_OFFSET)

#define	DMAC_SAR2					(DMAC_REGBASE + DMAC_SAR2_OFFSET)
#define	DMAC_DAR2					(DMAC_REGBASE + DMAC_DAR2_OFFSET)
#define	DMAC_DMATCR2				(DMAC_REGBASE + DMAC_DMATCR2_OFFSET)
#define	DMAC_CHCR2					(DMAC_REGBASE + DMAC_CHCR2_OFFSET)

#define	DMAC_SAR3					(DMAC_REGBASE + DMAC_SAR3_OFFSET)
#define	DMAC_DAR3					(DMAC_REGBASE + DMAC_DAR3_OFFSET)
#define	DMAC_DMATCR3				(DMAC_REGBASE + DMAC_DMATCR3_OFFSET)
#define	DMAC_CHCR3					(DMAC_REGBASE + DMAC_CHCR3_OFFSET)

#define	DMAC_DMAOR					(DMAC_REGBASE + DMAC_DMAOR_OFFSET)

//	DMA channel control register (DMAC_CHCR0 to 3)	

#define	DMAC_CHCR_SSA_RESERVED		0x00000000
#define	DMAC_CHCR_SSA_DYNAMIC_IO	0x20000000
#define	DMAC_CHCR_SSA_8_IO			0x40000000
#define	DMAC_CHCR_SSA_16_IO			0x60000000
#define	DMAC_CHCR_SSA_8_COMM		0x80000000
#define	DMAC_CHCR_SSA_16_COMM		0xA0000000
#define	DMAC_CHCR_SSA_8_ATTR		0xC0000000
#define	DMAC_CHCR_SSA_16_ATTR		0xE0000000

#define	DMAC_CHCR_STC_CS5			0x00000000
#define	DMAC_CHCR_STC_CS6			0x10000000

#define	DMAC_CHCR_DSA_RESERVED		0x00000000
#define	DMAC_CHCR_DSA_DYNAMIC_IO	0x02000000
#define	DMAC_CHCR_DSA_8_IO			0x04000000
#define	DMAC_CHCR_DSA_16_IO			0x06000000
#define	DMAC_CHCR_DSA_8_COMM		0x08000000
#define	DMAC_CHCR_DSA_16_COMM		0x0A000000
#define	DMAC_CHCR_DSA_8_ATTR		0x0C000000
#define	DMAC_CHCR_DSA_16_ATTR		0x0E000000

#define	DMAC_CHCR_DTC_CS5			0x00000000
#define	DMAC_CHCR_DTC_CS6			0x01000000

#define	DMAC_CHCR_DS_LOW_LEVEL		0x00000000
#define	DMAC_CHCR_DS_FALLING_EDGE	0x00080000

#define	DMAC_CHCR_RL_ACTIVE_HIGH	0x00000000
#define	DMAC_CHCR_RL_ACTIVE_LOW		0x00040000

#define	DMAC_CHCR_AM_READ_CYCLE		0x00000000
#define	DMAC_CHCR_AM_WRITE_CYCLE	0x00020000

#define	DMAC_CHCR_AL_ACTIVE_HIGH	0x00000000
#define	DMAC_CHCR_AL_ACTIVE_LOW		0x00010000

#define	DMAC_CHCR_DM_FIXED			0x00000000
#define	DMAC_CHCR_DM_INCREMENTED	0x00004000
#define	DMAC_CHCR_DM_DECREMENTED	0x00008000

#define	DMAC_CHCR_SM_FIXED			0x00000000
#define	DMAC_CHCR_SM_INCREMENTED	0x00001000
#define	DMAC_CHCR_SM_DECREMENTED	0x00002000

#define	DMAC_CHCR_RS_EX_DAM			0x00000000
#define	DMAC_CHCR_RS_EX_SAM_EAS_ED	0x00000200
#define	DMAC_CHCR_RS_EX_SAM_ED_EAS	0x00000300
#define	DMAC_CHCR_RS_AUTO_EAS_EAS	0x00000400
#define	DMAC_CHCR_RS_AUTO_EAS_OCP	0x00000500
#define	DMAC_CHCR_RS_AUTO_OCP_EAS	0x00000600
#define	DMAC_CHCR_RS_SCI1_EMPTY		0x00000800
#define	DMAC_CHCR_RS_SCI1_FULL		0x00000900
#define	DMAC_CHCR_RS_SCI2_EMPTY		0x00000A00
#define	DMAC_CHCR_RS_SCI2_FULL		0x00000B00
#define	DMAC_CHCR_RS_TMU2_EAS_EAS	0x00000C00
#define	DMAC_CHCR_RS_TMU2_EAS_OCP	0x00000D00
#define	DMAC_CHCR_RS_TMU2_OCP_EAS	0x00000E00

#define	DMAC_CHCR_TM_CYCLE_STEAL	0x00000000
#define	DMAC_CHCR_TM_BURST			0x00000080

#define	DMAC_CHCR_TS_64				0x00000000
#define	DMAC_CHCR_TS_8				0x00000010
#define	DMAC_CHCR_TS_16				0x00000020
#define	DMAC_CHCR_TS_32				0x00000030
#define	DMAC_CHCR_TS_32_BT			0x00000040

#define	DMAC_CHCR_IE_NOT_GENARATED	0x00000000
#define	DMAC_CHCR_IE_GENERATED		0x00000004

#define	DMAC_CHCR_TE_DMATCR_INCOMP	0x00000000
#define	DMAC_CHCR_TE_DMATCR_COMP	0x00000002

#define	DMAC_CHCR_DE_DISABLED		0x00000000
#define	DMAC_CHCR_DE_ENABLED		0x00000001

#define	DMAC_DMAOR_DDT				0x00008000
#define	DMAC_DMAOR_PR00				0x00000000
#define	DMAC_DMAOR_PR01				0x00000100
#define	DMAC_DMAOR_PR10				0x00000200
#define	DMAC_DMAOR_PR11				0x00000300
#define	DMAC_DMAOR_AE				0x00000004
#define	DMAC_DMAOR_NMFI				0x00000002
#define	DMAC_DMAOR_DME				0x00000001

//
// Clock Pulse Generator registers.
//

#define	CPG_REGBASE					0xFFC00000	// Frequency control register
#define CPG_REGSIZE					0x0014

#define	CPG_FRQCR_OFFSET			0x0000		// Frequency control register
#define	CPG_STBCR_OFFSET			0x0004		// Stanby control register
#define	CPG_WTCNT_OFFSET			0x0008		// Watchdog timer counter
#define	CPG_WTCSR_OFFSET			0x000C		// Watchdog timer control/status register
#define	CPG_STBCR2_OFFSET			0x0010		// Stanby control register 2

#define	CPG_FRQCR					(CPG_REGBASE + CPG_FRQCR_OFFSET)
#define	CPG_STBCR					(CPG_REGBASE + CPG_STBCR_OFFSET)
#define	CPG_WTCNT					(CPG_REGBASE + CPG_WTCNT_OFFSET)
#define	CPG_WTCSR					(CPG_REGBASE + CPG_WTCSR_OFFSET)
#define	CPG_STBCR2					(CPG_REGBASE + CPG_STBCR2_OFFSET)

// Frequency control register.

#define	CPG_FRQCR_CKOEN				0x0800		//Clock enable
#define	CPG_FRQCR_PLL1EN			0x0400		//PLL circuit 1 enable
#define	CPG_FRQCR_PLL2EN			0x0200		//PLL circuit 2 enable

#define	CPG_FRQCR_IFC				0x01C0		//Internal clock freq divider mask
#define	CPG_FRQCR_IFC_1				0x0000		// /1
#define	CPG_FRQCR_IFC_2				0x0040		// /2
#define	CPG_FRQCR_IFC_3				0x0080		// /3
#define	CPG_FRQCR_IFC_4				0x00C0		// /4
#define	CPG_FRQCR_IFC_6				0x0100		// /6
#define	CPG_FRQCR_IFC_8				0x0140		// /8

#define	CPG_FRQCR_BFC				0x0038		// Bus clock frequency division ratio mask
#define	CPG_FRQCR_BFC_1				0x0000		// /1
#define	CPG_FRQCR_BFC_2				0x0008		// /2
#define	CPG_FRQCR_BFC_3				0x0010		// /3
#define	CPG_FRQCR_BFC_4				0x0018		// /4
#define	CPG_FRQCR_BFC_6				0x0020		// /6
#define	CPG_FRQCR_BFC_8				0x0028		// /8

#define	CPG_FRQCR_PFC				0x0007		// Peripheral clock freq divider 2 rate mask
#define	CPG_FRQCR_PFC_2				0x0000		// /2
#define	CPG_FRQCR_PFC_3				0x0001		// /3
#define	CPG_FRQCR_PFC_4				0x0002		// /4
#define	CPG_FRQCR_PFC_6				0x0003		// /6
#define	CPG_FRQCR_PFC_8				0x0004		// /8	

// Standby control register

#define	CPG_STBCR_STBY				0x80		// Standby
#define	CPG_STBCR_PHZ				0x40		// Peripheral module pin high impedance
#define	CPG_STBCR_PPU				0x20		// Peripheral moduke pin pull up
#define	CPG_STBCR_MSTP4				0x10		// Module standby 4 (DMAC clock on/off)
#define	CPG_STBCR_MSTP3				0x08		// Module standby 3 (SCIF clock on/off)
#define	CPG_STBCR_MSTP2				0x04		// Module standby 2 (TMU clock on/off)
#define	CPG_STBCR_MSTP1				0x02		// Module standby 1 (RTC clock on/off)
#define	CPG_STBCR_MSTP0				0x01		// Module standby 0 (SCI clock on/off)

// Watchdog timer counter.

#define	CPG_WTCNT_COOKIE			0x5A00		// OR with new value before writing
#define	CPG_WTCNT_COUNT				0x00FF		// Watchdog timer counter mask	

// Watchdog timer control/status register.

#define	CPG_WTCSR_COOKIE			0xA500		// OR with new value before writing
#define	CPG_WTCSR_TME				0x0080		// Timer enable