sh4.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 1,105 行 · 第 1/4 页

#define	CPG_WTCSR_WT				0x0040		// Timer mode select, 1 <=> watchdog
#define	CPG_WTCSR_RSTS				0x0020		// Reset select
#define	CPG_WTCSR_WOVF				0x0010		// Watchdog timer overflow
#define	CPG_WTCSR_IOVF				0x0008		// Interval timer overflow

#define	CPG_WTCSR_CKS				0x0007		// Clock select, periph clock div ratio
#define	CPG_WTCSR_CKS_32			0x0000		// /32
#define	CPG_WTCSR_CKS_64			0x0001		// /64
#define	CPG_WTCSR_CKS_128			0x0002		// /128
#define	CPG_WTCSR_CKS_256			0x0003		// /256
#define	CPG_WTCSR_CKS_512			0x0004		// /512
#define	CPG_WTCSR_CKS_1024			0x0005		// /1024
#define	CPG_WTCSR_CKS_2048			0x0006		// /2048
#define	CPG_WTCSR_CKS_4096			0x0007		// /4096

// Stanby control register 2

#define	CPG_STBCR2_DSLP				0x80		// Deep sleep mode

//
// Real Time Clock control registers 
//

#define RTC_REGBASE					0xFFC80000
#define RTC_REGSIZE					0x0040

#define RTC_R64CNT_OFFSET			0x0000
#define RTC_RSECCNT_OFFSET			0x0004
#define RTC_RMINCNT_OFFSET			0x0008
#define RTC_RHRCNT_OFFSET			0x000C
#define RTC_RWKCNT_OFFSET			0x0010
#define RTC_RDAYCNT_OFFSET			0x0014
#define RTC_RMONCNT_OFFSET			0x0018
#define RTC_RYRCNT_OFFSET			0x001C
#define RTC_RSECAR_OFFSET			0x0020
#define RTC_RMINAR_OFFSET			0x0024
#define RTC_RHRAR_OFFSET			0x0028
#define RTC_RWKAR_OFFSET			0x002C
#define RTC_RDAYAR_OFFSET			0x0030
#define RTC_RMONAR_OFFSET			0x0034
#define RTC_RCR1_OFFSET				0x0038
#define RTC_RCR2_OFFSET				0x003c

#define RTC_R64CNT					RTC_REGBASE + RTC_R64CNT_OFFSET
#define RTC_RSECCNT					RTC_REGBASE + RTC_RSECCNT_OFFSET
#define RTC_RMINCNT					RTC_REGBASE + RTC_RMINCNT_OFFSET
#define RTC_RHRCNT					RTC_REGBASE + RTC_RHRCNT_OFFSET
#define RTC_RWKCNT					RTC_REGBASE + RTC_RWKCNT_OFFSET
#define RTC_RDAYCNT					RTC_REGBASE + RTC_RDAYCNT_OFFSET
#define RTC_RMONCNT					RTC_REGBASE + RTC_RMONCNT_OFFSET
#define RTC_RYRCNT					RTC_REGBASE + RTC_RYRCNT_OFFSET
#define RTC_RSECAR					RTC_REGBASE + RTC_RSECAR_OFFSET
#define RTC_RMINAR					RTC_REGBASE + RTC_RMINAR_OFFSET
#define RTC_RHRAR					RTC_REGBASE + RTC_RHRAR_OFFSET
#define RTC_RWKAR					RTC_REGBASE + RTC_RWKAR_OFFSET
#define RTC_RDAYAR					RTC_REGBASE + RTC_RDAYAR_OFFSET
#define RTC_RMONAR					RTC_REGBASE + RTC_RMONAR_OFFSET
#define RTC_RCR1					RTC_REGBASE + RTC_RCR1_OFFSET
#define RTC_RCR2					RTC_REGBASE + RTC_RCR2_OFFSET

// Second Alarm Register (RSECAR)

#define RTC_RSECAR_ENB				0x80

// Minute Alarm Register (RMINAR)

#define RTC_RMINAR_ENB				0x80

// Hour Alarm Register (RHRAR)

#define RTC_RHRAR_ENB				0x80

// Day of Week Alarm Register (RWKAR)

#define RTC_RWKAR_ENB				0x80

// Day Alarm Register (RDAYAR)

#define RTC_RDAYAR_ENB				0x80

// Month Alarm Register (RMONAR)

#define RTC_RMONAR_ENB				0x80

// RTC Control Register1 (RCR1)

#define RTC_RCR1_CF					0x80
#define RTC_RCR1_CIE				0x10
#define RTC_RCR1_AIE				0x08
#define RTC_RCR1_AF					0x01

// RTC Control Register2 (RCR2)

#define RTC_RCR2_PEF				0x80
#define RTC_RCR2_RES_2				0x70	//Periodic interrupt generated every 2 second  
#define RTC_RCR2_RES_1				0x60	//Periodic interrupt generated every 1 second  
#define RTC_RCR2_RES_1_2			0x50	//Periodic interrupt generated every 1/2 second  
#define RTC_RCR2_RES_1_4			0x40	//Periodic interrupt generated every 1/4 second  
#define RTC_RCR2_RES_1_16			0x30	//Periodic interrupt generated every 1/16 second  
#define RTC_RCR2_RES_1_64			0x20	//Periodic interrupt generated every 1/64 second  
#define RTC_RCR2_RES_1_256			0x10	//Periodic interrupt generated every 1/256 second  
#define RTC_RCR2_RES_NO_PINT		0x00	//NO periodic interrupt generation
#define RTC_RCR2_RTCEN				0x08
#define RTC_RCR2_ADJ				0x04
#define RTC_RCR2_RESET				0x02
#define RTC_RCR2_START				0x01

//
// Interrupt Controller registers
//

#define INTC_REGBASE				0xFFD00000
#define INTC_REGSIZE				0x0020

#define INTC_ICR_OFFSET				0x0000	// intr controll reg offset
#define INTC_IPRA_OFFSET			0x0004	// intr priority level A  offset
#define INTC_IPRB_OFFSET			0x0008	// intr priority level B  offset
#define INTC_IPRC_OFFSET			0x000C	// intr priority level C  offset

#define INTC_ICR					(INTC_REGBASE + INTC_ICR_OFFSET)
#define INTC_IPRA					(INTC_REGBASE + INTC_IPRA_OFFSET)
#define INTC_IPRB					(INTC_REGBASE + INTC_IPRB_OFFSET)
#define INTC_IPRC					(INTC_REGBASE + INTC_IPRC_OFFSET)

// Interrupt Control Register

#define INTC_ICR_IRL_MASK			0xFF7F
#define INTC_ICR_IRL_ENCODE			0x0000
#define INTC_ICR_IRL_INDEPENDENT	0x0080

// Interrupt Priority level setting Register A
 
#define INTC_IPRA_TMU0_MASK			0x0FFF
#define INTC_IPRA_TMU1_MASK			0xF0FF
#define INTC_IPRA_TMU2_MASK			0xFF0F
#define INTC_IPRA_RTC_MASK			0xFFF0

// Interrupt Priority level setting Register B
 
#define INTC_IPRB_WDT_MASK			0x0FFF
#define INTC_IPRB_REF_MASK			0xF0FF
#define INTC_IPRB_SCI_MASK			0xFF0F

// Interrupt Priority level setting Register C
 
#define INTC_IPRC_DMAC_MASK			0xF0FF
#define INTC_IPRC_SCIF_MASK			0xFF0F
#define INTC_IPRC_JTAG_MASK			0xFFF0

//
// Timer Unit registers
//

#define TMU_REGBASE					0xFFD80000
#define TMU_REGSIZE					0x0040

#define TMU_TOCR_OFFSET				0x0000				//common
#define TMU_TSTR_OFFSET				0x0004

#define TMU_TCOR0_OFFSET			0x0008				//TMU0
#define TMU_TCNT0_OFFSET			0x000C
#define TMU_TCR0_OFFSET				0x0010

#define TMU_TCOR1_OFFSET			0x0014				//TMU1
#define TMU_TCNT1_OFFSET			0x0018
#define TMU_TCR1_OFFSET				0x001C

#define TMU_TCOR2_OFFSET			0x0020				//TMU2
#define TMU_TCNT2_OFFSET			0x0024
#define TMU_TCR2_OFFSET				0x0028

#define TMU_TCPR2_OFFSET			0x002C

#define TMU_TOCR					(TMU_REGBASE + TMU_TOCR_OFFSET)
#define TMU_TSTR					(TMU_REGBASE + TMU_TSTR_OFFSET)

#define TMU_TCOR0					(TMU_REGBASE + TMU_TCOR0_OFFSET)
#define TMU_TCNT0					(TMU_REGBASE + TMU_TCNT0_OFFSET)
#define TMU_TCR0					(TMU_REGBASE + TMU_TCR0_OFFSET)

#define TMU_TCOR1					(TMU_REGBASE + TMU_TCOR1_OFFSET)
#define TMU_TCNT1					(TMU_REGBASE + TMU_TCNT1_OFFSET)
#define	TMU_TCR1					(TMU_REGBASE + TMU_TCR1_OFFSET)

#define TMU_TCOR2					(TMU_REGBASE + TMU_TCOR2_OFFSET)
#define	TMU_TCNT2					(TMU_REGBASE + TMU_TCNT2_OFFSET)
#define TMU_TCR2					(TMU_REGBASE + TMU_TCR2_OFFSET)

#define TMU_TCPR2					(TMU_REGBASE + TMU_TCPR2_OFFSET)

// Timer Start Register

#define TMU_TSTR_STR0				0x01
#define TMU_TSTR_STR1				0x02
#define TMU_TSTR_STR2				0x04

// Timer Control Register

#define TMU_TCR_UNF					0x100	// counter underflowed
#define TMU_TCR_UNIE				0x20	// underflow interrupt enable

#define TMU_TCR_RISE				0x00	// count on rising edge of clock
#define TMU_TCR_FALL				0x08	// count on falling edge of clock
#define TMU_TCR_BOTH				0x10	// count on both edges of clock

#define TMU_TCR_D4					0x00	// PERIPHERAL clock / 4
#define TMU_TCR_D16					0x01	// PERIPHERAL clock / 16
#define TMU_TCR_D64					0x02	// PERIPHERAL clock / 64
#define TMU_TCR_D256				0x03	// PERIPHERAL clock / 256
#define TMU_TCR_D1024				0x04	// PERIPHERAL clock / 1024
#define TMU_TCR_RTC					0x06	// real time clock output (16 kHz)
#define TMU_TCR_EXT					0x07	// external clock input

//
// Serial Communication Interface (SCI) 
//

#define SCI_REGBASE					0xFFE00000	// SH-4 control regs 
#define SCI_REGSIZE					0x0020	

#define SCI_SCSMR1_OFFSET			0x0000		// Serial Mode Register 
#define	SCI_SCBRR1_OFFSET			0x0004		// Bit rate register 
#define SCI_SCSCR1_OFFSET			0x0008		// Serial Control Register 
#define SCI_SCTDR1_OFFSET			0x000c		// transmit data register 
#define	SCI_SCSSR1_OFFSET			0x0010		// Serail Status Register 
#define SCI_SCRDR1_OFFSET			0x0014		// Receive Data register 
#define	SCI_SCSPTR1_OFFSET			0x001c		// Serial Port register 

#define SCI_SCSMR1					(SCI_REGBASE + SCI_SCSMR1_OFFSET)
#define	SCI_SCBRR1					(SCI_REGBASE + SCI_SCBRR1_OFFSET)
#define SCI_SCSCR1					(SCI_REGBASE + SCI_SCSCR1_OFFSET)
#define SCI_SCTDR1					(SCI_REGBASE + SCI_SCTDR1_OFFSET)
#define	SCI_SCSSR1					(SCI_REGBASE + SCI_SCSSR1_OFFSET)
#define SCI_SCRDR1					(SCI_REGBASE + SCI_SCRDR1_OFFSET)
#define	SCI_SCSPTR1					(SCI_REGBASE + SCI_SCSPTR1_OFFSET)

//
// Serial Communication Interface with FIFO (SCIF) 
//

#define SCIF_REGBASE				0xFFE80000	// SH-4 control regs 
#define SCIF_REGSIZE				0x0028	

#define SCIF_SCSMR2_OFFSET			0x0000		// Serial Mode Register 
#define	SCIF_SCBRR2_OFFSET			0x0004		// Bit rate register 
#define SCIF_SCSCR2_OFFSET			0x0008		// Serial Control Register 
#define SCIF_SCFTDR2_OFFSET			0x000c		// transmit FIFO data register 
#define	SCIF_SCFSR2_OFFSET			0x0010		// Serail Status Register 
#define SCIF_SCFRDR2_OFFSET			0x0014		// Receive Data FIFO register 
#define	SCIF_SCFCR2_OFFSET			0x0018		// FIFO Control Register 
#define	SCIF_SCFDR2_OFFSET			0x001c		// FIFO Data Count set register 
#define	SCIF_SCSPTR2_OFFSET			0x0020		// FIFO Data Count set register 
#define	SCIF_SCLSR2_OFFSET			0x0024		// FIFO Data Count set register 

#define SCIF_SCSMR2					(SCIF_REGBASE + SCIF_SCSMR2_OFFSET)
#define	SCIF_SCBRR2					(SCIF_REGBASE + SCIF_SCBRR2_OFFSET)
#define SCIF_SCSCR2					(SCIF_REGBASE + SCIF_SCSCR2_OFFSET)
#define SCIF_SCFTDR2				(SCIF_REGBASE + SCIF_SCFTDR2_OFFSET)
#define	SCIF_SCFSR2					(SCIF_REGBASE + SCIF_SCFSR2_OFFSET)
#define SCIF_SCFRDR2				(SCIF_REGBASE + SCIF_SCFRDR2_OFFSET)
#define	SCIF_SCFCR2					(SCIF_REGBASE + SCIF_SCFCR2_OFFSET)
#define	SCIF_SCFDR2					(SCIF_REGBASE + SCIF_SCFDR2_OFFSET)
#define	SCIF_SCSPTR2				(SCIF_REGBASE + SCIF_SCSPTR2_OFFSET)
#define	SCIF_SCLSR2					(SCIF_REGBASE + SCIF_SCLSR2_OFFSET)

//
// The SR reg, puts us in priviledged mode, and blocks all interrupts
//

#define	TM_SR						0x70000000
#define EXPEVT						0xFF000024
#define INTEVT						0xff000028
#endif