sh4.h
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 1,105 行 · 第 1/4 页
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#define BSC_WCR2_A5W_6 0x02000000 // Area 5 has 6 wait states
#define BSC_WCR2_A5W_9 0x02800000 // Area 5 has 9 wait states
#define BSC_WCR2_A5W_12 0x03000000 // Area 5 has 12 wait states
#define BSC_WCR2_A5W_15 0x03800000 // Area 5 has 15 wait states
#define BSC_WCR2_A5B 0x00700000 // Area 5 burst sycle mask
#define BSC_WCR2_A5B_0 0x00000000 // Area 5 has 0 states per data transfer
#define BSC_WCR2_A5B_1 0x00100000 // Area 5 has 1 states per data transfer
#define BSC_WCR2_A5B_2 0x00200000 // Area 5 has 2 states per data transfer
#define BSC_WCR2_A5B_3 0x00300000 // Area 5 has 3 states per data transfer
#define BSC_WCR2_A5B_4 0x00400000 // Area 5 has 4 states per data transfer
#define BSC_WCR2_A5B_5 0x00500000 // Area 5 has 5 states per data transfer
#define BSC_WCR2_A5B_6 0x00600000 // Area 5 has 6 states per data transfer
#define BSC_WCR2_A5B_7 0x00700000 // Area 5 has 7 states per data transfer
#define BSC_WCR2_A4W 0x000E0000 // Area 4 wait state mask
#define BSC_WCR2_A4W_0 0x00000000 // Area 4 has 0 wait states
#define BSC_WCR2_A4W_1 0x00020000 // Area 4 has 1 wait states
#define BSC_WCR2_A4W_2 0x00040000 // Area 4 has 2 wait states
#define BSC_WCR2_A4W_3 0x00060000 // Area 4 has 3 wait states
#define BSC_WCR2_A4W_6 0x00080000 // Area 4 has 6 wait states
#define BSC_WCR2_A4W_9 0x000A0000 // Area 4 has 9 wait states
#define BSC_WCR2_A4W_12 0x000C0000 // Area 4 has 12 wait states
#define BSC_WCR2_A4W_15 0x000E0000 // Area 4 has 15 wait states
// When Normal Memory is Used
#define BSC_WCR2_A3W_NORMAL 0x0000E000 // Area 3 wait state mask
#define BSC_WCR2_A3W_NORMAL_0 0x00000000 // Area 3 has 0 wait states
#define BSC_WCR2_A3W_NORMAL_1 0x00002000 // Area 3 has 1 wait states
#define BSC_WCR2_A3W_NORMAL_2 0x00004000 // Area 3 has 2 wait states
#define BSC_WCR2_A3W_NORMAL_3 0x00006000 // Area 3 has 3 wait states
#define BSC_WCR2_A3W_NORMAL_6 0x00008000 // Area 3 has 6 wait states
#define BSC_WCR2_A3W_NORMAL_9 0x0000A000 // Area 3 has 9 wait states
#define BSC_WCR2_A3W_NORMAL_12 0x0000C000 // Area 3 has 12 wait states
#define BSC_WCR2_A3W_NORMAL_15 0x0000E000 // Area 3 has 15 wait states
// When DRAM, Synchronours DRAM is Used
#define BSC_WCR2_A3W_DRAM 0x0000E000 // Area 3 assertion width mask
#define BSC_WCR2_A3W_DRAM_1 0x00000000 // Area 3 has 1 assertion width
#define BSC_WCR2_A3W_DRAM_2 0x00002000 // Area 3 has 2 assertion width
#define BSC_WCR2_A3W_DRAM_3 0x00004000 // Area 3 has 3 assertion width
#define BSC_WCR2_A3W_DRAM_4 0x00006000 // Area 3 has 4 assertion width
#define BSC_WCR2_A3W_DRAM_7 0x00008000 // Area 3 has 7 assertion width
#define BSC_WCR2_A3W_DRAM_10 0x0000A000 // Area 3 has 10 assertion width
#define BSC_WCR2_A3W_DRAM_13 0x0000C000 // Area 3 has 13 assertion width
#define BSC_WCR2_A3W_DRAM_16 0x0000E000 // Area 3 has 16 assertion width
// When Normal Memory is Used
#define BSC_WCR2_A2W_NORMAL 0x00000E00 // Area 2 wait state mask
#define BSC_WCR2_A2W_NORMAL_0 0x00000000 // Area 2 has 0 wait states
#define BSC_WCR2_A2W_NORMAL_1 0x00000200 // Area 2 has 1 wait states
#define BSC_WCR2_A2W_NORMAL_2 0x00000400 // Area 2 has 2 wait states
#define BSC_WCR2_A2W_NORMAL_3 0x00000600 // Area 2 has 3 wait states
#define BSC_WCR2_A2W_NORMAL_6 0x00000800 // Area 2 has 6 wait states
#define BSC_WCR2_A2W_NORMAL_9 0x00000A00 // Area 2 has 9 wait states
#define BSC_WCR2_A2W_NORMAL_12 0x00000C00 // Area 2 has 12 wait states
#define BSC_WCR2_A2W_NORMAL_15 0x00000E00 // Area 2 has 15 wait states
// When DRAM, Synchronours DRAM is Used
#define BSC_WCR2_A2W_DRAM 0x00000E00 // Area 2 assertion width mask
#define BSC_WCR2_A2W_DRAM_1 0x00000000 // Area 2 has 1 assertion width
#define BSC_WCR2_A2W_DRAM_2 0x00000200 // Area 2 has 2 assertion width
#define BSC_WCR2_A2W_DRAM_3 0x00000400 // Area 2 has 3 assertion width
#define BSC_WCR2_A2W_DRAM_4 0x00000600 // Area 2 has 4 assertion width
#define BSC_WCR2_A2W_DRAM_7 0x00000800 // Area 2 has 7 assertion width
#define BSC_WCR2_A2W_DRAM_10 0x00000A00 // Area 2 has 10 assertion width
#define BSC_WCR2_A2W_DRAM_13 0x00000C00 // Area 2 has 13 assertion width
#define BSC_WCR2_A2W_DRAM_16 0x00000E00 // Area 2 has 16 assertion width
#define BSC_WCR2_A1W 0x000001C0 // Area 1 wait state mask
#define BSC_WCR2_A1W_0 0x00000000 // Area 1 has 0 wait states
#define BSC_WCR2_A1W_1 0x00000040 // Area 1 has 1 wait states
#define BSC_WCR2_A1W_2 0x00000080 // Area 1 has 2 wait states
#define BSC_WCR2_A1W_3 0x000000C0 // Area 1 has 3 wait states
#define BSC_WCR2_A1W_6 0x00000100 // Area 1 has 6 wait states
#define BSC_WCR2_A1W_9 0x00000140 // Area 1 has 9 wait states
#define BSC_WCR2_A1W_12 0x00000180 // Area 1 has 12 wait states
#define BSC_WCR2_A1W_15 0x000001C0 // Area 1 has 15 wait states
#define BSC_WCR2_A0W 0x00000038 // Area 0 wait state mask
#define BSC_WCR2_A0W_0 0x00000000 // Area 0 has 0 wait states
#define BSC_WCR2_A0W_1 0x00000008 // Area 0 has 1 wait states
#define BSC_WCR2_A0W_2 0x00000010 // Area 0 has 2 wait states
#define BSC_WCR2_A0W_3 0x00000018 // Area 0 has 3 wait states
#define BSC_WCR2_A0W_6 0x00000020 // Area 0 has 6 wait states
#define BSC_WCR2_A0W_9 0x00000028 // Area 0 has 9 wait states
#define BSC_WCR2_A0W_12 0x00000030 // Area 0 has 12 wait states
#define BSC_WCR2_A0W_15 0x00000038 // Area 0 has 15 wait states
#define BSC_WCR2_A0B 0x00000007 // Area 0 wait state mask
#define BSC_WCR2_A0B_0 0x00000000 // Area 0 has 0 wait states
#define BSC_WCR2_A0B_1 0x00000001 // Area 0 has 1 wait states
#define BSC_WCR2_A0B_2 0x00000002 // Area 0 has 2 wait states
#define BSC_WCR2_A0B_3 0x00000003 // Area 0 has 3 wait states
#define BSC_WCR2_A0B_4 0x00000004 // Area 0 has 4 wait states
#define BSC_WCR2_A0B_5 0x00000005 // Area 0 has 5 wait states
#define BSC_WCR2_A0B_6 0x00000006 // Area 0 has 6 wait states
#define BSC_WCR2_A0B_7 0x00000007 // Area 0 has 7 wait states
// WCR3 Wait state control register 3 fields.
#define BSC_WCR3_A6S 0x04000000 // Area 6 write strobe setup time mask
#define BSC_WCR3_A6S_0 0x00000000 // Area 6 has 0 wait inserted in setup
#define BSC_WCR3_A6S_1 0x04000000 // Area 6 has 1 wait inserted in setup
#define BSC_WCR3_A6H 0x03000000 // Area 6 data hold time mask
#define BSC_WCR3_A6H_0 0x00000000 // Area 6 has 0 wait inserted in hold
#define BSC_WCR3_A6H_1 0x01000000 // Area 6 has 1 wait inserted in hold
#define BSC_WCR3_A6H_2 0x02000000 // Area 6 has 2 wait inserted in hold
#define BSC_WCR3_A6H_3 0x03000000 // Area 6 has 3 wait inserted in hold
#define BSC_WCR3_A5S 0x00400000 // Area 5 write strobe setup time mask
#define BSC_WCR3_A5S_0 0x00000000 // Area 5 has 0 wait inserted in setup
#define BSC_WCR3_A5S_1 0x00400000 // Area 5 has 1 wait inserted in setup
#define BSC_WCR3_A5H 0x00300000 // Area 5 data hold time mask
#define BSC_WCR3_A5H_0 0x00000000 // Area 5 has 0 wait inserted in hold
#define BSC_WCR3_A5H_1 0x00100000 // Area 5 has 1 wait inserted in hold
#define BSC_WCR3_A5H_2 0x00200000 // Area 5 has 2 wait inserted in hold
#define BSC_WCR3_A5H_3 0x00300000 // Area 5 has 3 wait inserted in hold
#define BSC_WCR3_A4S 0x00040000 // Area 4 write strobe setup time mask
#define BSC_WCR3_A4S_0 0x00000000 // Area 4 has 0 wait inserted in setup
#define BSC_WCR3_A4S_1 0x00040000 // Area 4 has 1 wait inserted in setup
#define BSC_WCR3_A4H 0x00030000 // Area 4 data hold time mask
#define BSC_WCR3_A4H_0 0x00000000 // Area 4 has 0 wait inserted in hold
#define BSC_WCR3_A4H_1 0x00010000 // Area 4 has 1 wait inserted in hold
#define BSC_WCR3_A4H_2 0x00020000 // Area 4 has 2 wait inserted in hold
#define BSC_WCR3_A4H_3 0x00030000 // Area 4 has 3 wait inserted in hold
#define BSC_WCR3_A3S 0x00004000 // Area 3 write strobe setup time mask
#define BSC_WCR3_A3S_0 0x00000000 // Area 3 has 0 wait inserted in setup
#define BSC_WCR3_A3S_1 0x00004000 // Area 3 has 1 wait inserted in setup
#define BSC_WCR3_A3H 0x00003000 // Area 3 data hold time mask
#define BSC_WCR3_A3H_0 0x00000000 // Area 3 has 0 wait inserted in hold
#define BSC_WCR3_A3H_1 0x00001000 // Area 3 has 1 wait inserted in hold
#define BSC_WCR3_A3H_2 0x00002000 // Area 3 has 2 wait inserted in hold
#define BSC_WCR3_A3H_3 0x00003000 // Area 3 has 3 wait inserted in hold
#define BSC_WCR3_A2S 0x00000400 // Area 2 write strobe setup time mask
#define BSC_WCR3_A2S_0 0x00000000 // Area 2 has 0 wait inserted in setup
#define BSC_WCR3_A2S_1 0x00000400 // Area 2 has 1 wait inserted in setup
#define BSC_WCR3_A2H 0x00000300 // Area 2 data hold time mask
#define BSC_WCR3_A2H_0 0x00000000 // Area 2 has 0 wait inserted in hold
#define BSC_WCR3_A2H_1 0x00000100 // Area 2 has 1 wait inserted in hold
#define BSC_WCR3_A2H_2 0x00000200 // Area 2 has 2 wait inserted in hold
#define BSC_WCR3_A2H_3 0x00000300 // Area 2 has 3 wait inserted in hold
#define BSC_WCR3_A1S 0x00000040 // Area 1 write strobe setup time mask
#define BSC_WCR3_A1S_0 0x00000000 // Area 1 has 0 wait inserted in setup
#define BSC_WCR3_A1S_1 0x00000040 // Area 1 has 1 wait inserted in setup
#define BSC_WCR3_A1H 0x00000030 // Area 1 data hold time mask
#define BSC_WCR3_A1H_0 0x00000000 // Area 1 has 0 wait inserted in hold
#define BSC_WCR3_A1H_1 0x00000010 // Area 1 has 1 wait inserted in hold
#define BSC_WCR3_A1H_2 0x00000020 // Area 1 has 2 wait inserted in hold
#define BSC_WCR3_A1H_3 0x00000030 // Area 1 has 3 wait inserted in hold
#define BSC_WCR3_A0S 0x00000004 // Area 0 write strobe setup time mask
#define BSC_WCR3_A0S_0 0x00000000 // Area 0 has 0 wait inserted in setup
#define BSC_WCR3_A0S_1 0x00000004 // Area 0 has 1 wait inserted in setup
#define BSC_WCR3_A0H 0x00000003 // Area 0 data hold time mask
#define BSC_WCR3_A0H_0 0x00000000 // Area 0 has 0 wait inserted in hold
#define BSC_WCR3_A0H_1 0x00000001 // Area 0 has 1 wait inserted in hold
#define BSC_WCR3_A0H_2 0x00000002 // Area 0 has 2 wait inserted in hold
#define BSC_WCR3_A0H_3 0x00000003 // Area 0 has 3 wait inserted in hold
// MCR Individual memory control register (RAS/CAS timing and burst control for
// DRAM, SRAM and PSRAM, address multiplexing, and refresh control.
#define BSC_MCR_RASD 0x10000000 // RAS down mode
#define BSC_MCR_MRSET 0x40000000 // Mode register set
#define BSC_MCR_TRC 0x38000000 // RAS precharge time mask
#define BSC_MCR_TRC_0 0x00000000 // 0 cycle
#define BSC_MCR_TRC_3 0x08000000 // 3 cycle
#define BSC_MCR_TRC_6 0x10000000 // 6 cycles
#define BSC_MCR_TRC_9 0x18000000 // 9 cycles
#define BSC_MCR_TRC_12 0x20000000 // 12 cycles
#define BSC_MCR_TRC_15 0x28000000 // 15 cycles
#define BSC_MCR_TRC_18 0x30000000 // 18 cycles
#define BSC_MCR_TRC_21 0x38000000 // 21 cycles
#define BSC_MCR_TCAS 0x00800000 // CAS Assertion Period 0:1, 1:2
#define BSC_MCR_TPC 0x00380000 // RAS precharge period mask
#define BSC_MCR_TPC_0 0x00000000 // 0 cycle
#define BSC_MCR_TPC_1 0x00080000 // 1 cycle
#define BSC_MCR_TPC_2 0x00100000 // 2 cycles
#define BSC_MCR_TPC_3 0x00180000 // 3 cycles
#define BSC_MCR_TPC_4 0x00200000 // 4 cycles
#define BSC_MCR_TPC_5 0x00280000 // 5 cycles
#define BSC_MCR_TPC_6 0x00300000 // 6 cycles
#define BSC_MCR_TPC_7 0x00380000 // 7 cycles
#define BSC_MCR_RCD 0x00030000 // RAS-CAS delay mask
#define BSC_MCR_RCD_2 0x00000000 // 2 cycle
#define BSC_MCR_RCD_3 0x00010000 // 3 cycles
#define BSC_MCR_RCD_4 0x00020000 // 4 cycles
#define BSC_MCR_RCD_5 0x00030000 // 5 cycles
#define BSC_MCR_TRWL 0x0000e000 // Write-precharge delay
#define BSC_MCR_TRWL_1 0x00000000 // 1 cycle
#define BSC_MCR_TRWL_2 0x00002000 // 2 cycles
#define BSC_MCR_TRWL_3 0x00004000 // 3 cycles
#define BSC_MCR_TRWL_4 0x00006000 // 4 cycles
#define BSC_MCR_TRWL_5 0x00008000 // 5 cycles
#define BSC_MCR_TRAS 0x00001C00 // RAS assertion period mask
#define BSC_MCR_TRAS_2 0x00000000 // 2 cycles
#define BSC_MCR_TRAS_3 0x00000400 // 3 cycles
#define BSC_MCR_TRAS_4 0x00000800 // 4 cycles
#define BSC_MCR_TRAS_5 0x00000C00 // 5 cycles
#define BSC_MCR_TRAS_6 0x00001000 // 6 cycles
#define BSC_MCR_TRAS_7 0x00001400 // 7 cycles
#define BSC_MCR_TRAS_8 0x00001800 // 8 cycles
#define BSC_MCR_TRAS_9 0x00001C00 // 9 cycles
#define BSC_MCR_BE 0x00000200 // Burst enable
#define BSC_MCR_SZ 0x00000180 // Memory data size mask
#define BSC_MCR_SZ_64 0x00000000 // Memory data size 64
#define BSC_MCR_SZ_16 0x00000100 // Memory data size 16
#define BSC_MCR_SZ_32 0x00000180 // Memory data size 32
#define BSC_MCR_AMXEXT 0x00000040 // Address multiplexing
#define BSC_MCR_AMX 0x00000038 // Address multiplex mask
#define BSC_MCR_AMX_8 0x00000000 // 8-bit column address product
#define BSC_MCR_AMX_9 0x00000008 // 9-bit column address product
#define BSC_MCR_AMX_10 0x00000010 // 10-bit column address product
#define BSC_MCR_AMX_11 0x00000018 // 11-bit column address product
#define BSC_MCR_AMX_12 0x00000020 // 12-bit column address product
#define BSC_MCR_RFSH 0x00000004 // Refresh enable
#define BSC_MCR_RMODE 0x00000002 // Refresh mode, 0 => ordinary, 1 => self
#define BSC_MCR_EDOMODE 0x00000001 // EDO mode 1:EDO, 0:SDRAM or SGRAM
// PCMCIA Control Register(PCR)
#define BSC_PCR_A5PCW 0xC000 // PCMCIA area 5 wait mask
#define BSC_PCR_A5PCW_0 0x0000 // Area 5 has 0 wait inserted
#define BSC_PCR_A5PCW_15 0x4000 // Area 5 has 15 wait inserted
#define BSC_PCR_A5PCW_30 0x8000 // Area 5 has 30 wait inserted
#define BSC_PCR_A5PCW_50 0xC000 // Area 5 has 50 wait inserted
#define BSC_PCR_A6PCW 0x3000 // PCMCIA area 6 wait mask
#define BSC_PCR_A6PCW_0 0x0000 // Area 6 has 0 wait inserted
#define BSC_PCR_A6PCW_15 0x1000 // Area 6 has 15 wait inserted
#define BSC_PCR_A6PCW_30 0x2000 // Area 6 has 30 wait inserted
#define BSC_PCR_A6PCW_50 0x3000 // Area 6 has 50 wait inserted
#define BSC_PCR_A5TED 0x0E00 // PCMCIA area 5 address assertion delay mask
#define BSC_PCR_A5TED_0 0x0000 // Area 5 has 0 wait inserted
#define BSC_PCR_A5TED_1 0x0200 // Area 5 has 1 wait inserted
#define BSC_PCR_A5TED_2 0x0400 // Area 5 has 2 wait inserted
#define BSC_PCR_A5TED_3 0x0600 // Area 5 has 3 wait inserted
#define BSC_PCR_A5TED_6 0x0800 // Area 5 has 6 wait inserted
#define BSC_PCR_A5TED_9 0x0A00 // Area 5 has 9 wait inserted
#define BSC_PCR_A5TED_12 0x0C00 // Area 5 has 12 wait inserted
#define BSC_PCR_A5TED_15 0x0E00 // Area 5 has 15 wait inserted
#define BSC_PCR_A6TED 0x01C0 // PCMCIA area 6 address assertion delay mask
#define BSC_PCR_A6TED_0 0x0000 // Area 6 has 0 wait inserted
#define BSC_PCR_A6TED_1 0x0040 // Area 6 has 1 wait inserted
#define BSC_PCR_A6TED_2 0x0080 // Area 6 has 2 wait inserted
#define BSC_PCR_A6TED_3 0x00C0 // Area 6 has 3 wait inserted
#define BSC_PCR_A6TED_6 0x0100 // Area 6 has 6 wait inserted
#define BSC_PCR_A6TED_9 0x0140 // Area 6 has 9 wait inserted
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