sdrm_par.v

这是使用VERILOG语言

// Xilinx Verilog produced by program ngd2ver C.16
// Command: -w sdrm_par sdrm_par.v 
// Options: -w -log ngd2ver.log -ti uut 
// Date: Tue Jun 29 10:40:22 1999 
// Input file: sdrm_par.nga
// Output file: sdrm_par.v
// Tmp file: /var/tmp/xil_CAA0xlb7T
// Design name: Synopsys_edif
// Xilinx: /tools/cheshire/denali/verify/xfndry/rtf/C_current
// # of Modules: 1
// Device: v300bg432-6

// The output of ngd2ver is a simulation model. This file cannot be synthesized,
// or used in any other manner other than simulation. This netlist uses simulation
// primitives which may not represent the true implementation of the device, however
// the netlist is functionally correct. Do not modify this file.

`timescale 1 ns/1 ps

  module Synopsys_edif (
    Clk_SDp, sd_we, Clk_FBp, we_rn, sd_cs1, sd_cs2, Clkp, sd_ba, data_addr_n, 
    sd_ras, Reset, sd_cas, sd_cke, AD, sd_dqm, sd_add, sd_data
  );
    output Clk_SDp;
    output sd_we;
    input Clk_FBp;
    input we_rn;
    output sd_cs1;
    output sd_cs2;
    input Clkp;
    output sd_ba;
    input data_addr_n;
    output sd_ras;
    input Reset;
    output sd_cas;
    output sd_cke;
    inout [31:0] AD;
    output [3:0] sd_dqm;
    output [10:0] sd_add;
    inout [31:0] sd_data;
    wire Clk_i;
    wire Locked_i;
    wire AD_tri;
    wire Clk0A;
    wire sd_we_op;
    wire Clk_FB;
    wire we_rn_i;
    wire Clk;
    wire sd_ba_op;
    wire data_addr_n_reg;
    wire sd_ras_op;
    wire Reset_i;
    wire sd_cas_op;
    wire Clk0B;
    wire Clk0C;
    wire Clk_j;
    wire Locked1;
    wire Locked2;
    wire \sdrm_t/ref_cntr/sub_59/A_CY_1/O ;
    wire \sdrm_t/ref_cntr/sub_59/A_CY_3/O ;
    wire \sdrm_t/ref_cntr/sub_59/A_CY_5/O ;
    wire \sdrm_t/ref_cntr/sub_59/A_CY_7/O ;
    wire \sdrm_t/ref_cntr/sub_59/A_CY_9/O ;
    wire \sdrm_t/ref_cntr/sub_59/A_CY_11/O ;
    wire \sdrm_t/ref_cntr/sub_59/A_CY_13/O ;
    wire \sdrm_t/brst_cntr/sub_55/A_CY_1/O ;
    wire \sdrm_t/ki_cntr/sub_54/A_CY_1/O ;
    wire \sdrm_t/n498 ;
    wire \sdrm_t/n493 ;
    wire \sdrm_t/n453 ;
    wire \sdrm_t/n452 ;
    wire \sdrm_t/n451 ;
    wire \sdrm_t/n450 ;
    wire \sdrm_t/n449 ;
    wire \sdrm_t/sdrm_st/c_write_c ;
    wire \sdrm_t/sdrm_st/state[13] ;
    wire \sdrm_t/sdrm_st/state[6] ;
    wire \sdrm_t/n481 ;
    wire \sdrm_t/sdrm_st/state[11] ;
    wire \sdrm_t/n488 ;
    wire \sdrm_t/n448 ;
    wire \sdrm_t/n447 ;
    wire \sdrm_t/n446 ;
    wire \sdrm_t/n445 ;
    wire \sdrm_t/sdrm_st/state[5] ;
    wire \sdrm_t/sdrm_st/state[3] ;
    wire \sdrm_t/sdrm_st/state[8] ;
    wire \sdrm_t/sdrm_st/state[2] ;
    wire \sdrm_t/n444 ;
    wire \sdrm_t/n478 ;
    wire \sdrm_t/ld_brst ;
    wire \sdrm_t/n479 ;
    wire \sdrm_t/pre_sd_ready ;
    wire \sdrm_t/sdrm_st/state[9] ;
    wire \sdrm_t/pre_sd_ras_p ;
    wire \sdrm_t/sdrm_st/state[1] ;
    wire \sdrm_t/sd_add_mx ;
    wire \sdrm_t/clr_ref ;
    wire \sdrm_t/n480 ;
    wire \sdrm_t/ref_cntr/n_113 ;
    wire \sdrm_t/sdrm_st/state[7] ;
    wire \sdrm_t/n482 ;
    wire \sdrm_t/n486 ;
    wire \sdrm_t/pre_ld_rcd ;
    wire \sdrm_t/ld_rcd ;
    wire \sdrm_t/ld_cslt ;
    wire \sdrm_t/n494 ;
    wire \sdrm_t/n497 ;
    wire \sdrm_t/n495 ;
    wire \sdrm_t/n496 ;
    wire \sdrm_t/n483 ;
    wire \sdrm_t/n484 ;
    wire auto_ref_in;
    wire \sdrm_t/n485 ;
    wire \sdrm_t/n443 ;
    wire \sdrm_t/n442 ;
    wire \sdrm_t/n441 ;
    wire \sdrm_t/n440 ;
    wire \sdrm_t/n439 ;
    wire \sdrm_t/n489 ;
    wire \sdrm_t/n490 ;
    wire \sdrm_t/n491 ;
    wire \sdrm_t/n492 ;
    wire \sdrm_t/n438 ;
    wire \sdrm_t/pre_ad_tri ;
    wire \sys_int/n_431 ;
    wire \sdrm_t/n487 ;
    wire GLOBAL_LOGIC1;
    wire GLOBAL_LOGIC0;
    wire \sdrm_t/pre_locked ;
    wire GLOBAL_LOGIC0_0;
    wire GLOBAL_LOGIC0_1;
    wire GLOBAL_LOGIC0_2;
    wire GLOBAL_LOGIC0_3;
    wire GLOBAL_LOGIC0_4;
    wire GLOBAL_LOGIC0_5;
    wire GLOBAL_LOGIC0_6;
    wire GLOBAL_LOGIC0_7;
    wire GLOBAL_LOGIC0_8;
    wire GLOBAL_LOGIC0_9;
    wire GLOBAL_LOGIC0_10;
    wire GLOBAL_LOGIC0_11;
    wire GLOBAL_LOGIC0_12;
    wire GLOBAL_LOGIC0_13;
    wire GLOBAL_LOGIC0_14;
    wire GLOBAL_LOGIC0_15;
    wire GLOBAL_LOGIC0_16;
    wire GLOBAL_LOGIC0_17;
    wire GLOBAL_LOGIC0_18;
    wire GLOBAL_LOGIC0_19;
    wire GLOBAL_LOGIC0_20;
    wire GLOBAL_LOGIC0_21;
    wire GLOBAL_LOGIC0_22;
    wire GLOBAL_LOGIC0_23;
    wire GLOBAL_LOGIC0_24;
    wire GLOBAL_LOGIC0_25;
    wire GLOBAL_LOGIC0_26;
    wire GLOBAL_LOGIC0_27;
    wire GLOBAL_LOGIC0_28;
    wire GLOBAL_LOGIC0_29;
    wire GLOBAL_LOGIC0_30;
    wire GLOBAL_LOGIC0_31;
    wire GLOBAL_LOGIC0_32;
    wire GLOBAL_LOGIC1_0;
    wire GLOBAL_LOGIC1_1;
    wire GLOBAL_LOGIC1_2;
    wire GLOBAL_LOGIC1_3;
    wire GLOBAL_LOGIC1_4;
    wire GLOBAL_LOGIC1_5;
    wire GLOBAL_LOGIC1_6;
    wire GLOBAL_LOGIC1_7;
    wire GLOBAL_LOGIC1_8;
    wire GLOBAL_LOGIC1_9;
    wire GLOBAL_LOGIC1_10;
    wire GLOBAL_LOGIC1_11;
    wire GLOBAL_LOGIC1_12;
    wire GLOBAL_LOGIC1_13;
    wire GLOBAL_LOGIC1_14;
    wire GLOBAL_LOGIC1_15;
    wire GLOBAL_LOGIC1_16;
    wire GLOBAL_LOGIC1_17;
    wire GLOBAL_LOGIC1_18;
    wire GLOBAL_LOGIC1_19;
    wire GLOBAL_LOGIC1_20;
    wire GLOBAL_LOGIC1_21;
    wire GLOBAL_LOGIC1_22;
    wire GLOBAL_LOGIC1_23;
    wire GLOBAL_LOGIC1_24;
    wire GLOBAL_LOGIC1_25;
    wire GLOBAL_LOGIC1_26;
    wire GLOBAL_LOGIC1_27;
    wire GLOBAL_LOGIC1_28;
    wire GLOBAL_LOGIC1_29;
    wire GLOBAL_LOGIC1_30;
    wire GLOBAL_LOGIC1_31;
    wire GLOBAL_LOGIC1_32;
    wire \AD[18]/SRNOT ;
    wire \AD[18]/IBUF ;
    wire \AD[18]/OQ ;
    wire \AD[18]/KEEPER ;
    wire \AD[18]/OUTBUF_GTS_AND ;
    wire \AD[18]/IFF/ASYNC_FF_GSR_OR ;
    wire \AD[18]/OFF/ASYNC_FF_GSR_OR ;
    wire \AD[26]/SRNOT ;
    wire \AD[26]/IBUF ;
    wire \AD[26]/OQ ;
    wire \AD[26]/KEEPER ;
    wire \AD[26]/OUTBUF_GTS_AND ;
    wire \AD[26]/IFF/ASYNC_FF_GSR_OR ;
    wire \AD[26]/OFF/ASYNC_FF_GSR_OR ;
    wire \AD[8]/SRNOT ;
    wire \AD[8]/IBUF ;
    wire \AD[8]/OQ ;
    wire \AD[8]/KEEPER ;
    wire \AD[8]/OUTBUF_GTS_AND ;
    wire \AD[8]/IFF/ASYNC_FF_GSR_OR ;
    wire \AD[8]/OFF/ASYNC_FF_GSR_OR ;
    wire \AD[27]/SRNOT ;
    wire \AD[27]/IBUF ;
    wire \AD[27]/OQ ;
    wire \AD[27]/KEEPER ;
    wire \AD[27]/OUTBUF_GTS_AND ;
    wire \AD[27]/IFF/ASYNC_FF_GSR_OR ;
    wire \AD[27]/OFF/ASYNC_FF_GSR_OR ;
    wire \AD[19]/SRNOT ;
    wire \AD[19]/IBUF ;
    wire \AD[19]/OQ ;
    wire \AD[19]/KEEPER ;
    wire \AD[19]/OUTBUF_GTS_AND ;
    wire \AD[19]/IFF/ASYNC_FF_GSR_OR ;
    wire \AD[19]/OFF/ASYNC_FF_GSR_OR ;
    wire \AD[9]/SRNOT ;
    wire \AD[9]/IBUF ;
    wire \AD[9]/OQ ;
    wire \AD[9]/KEEPER ;
    wire \AD[9]/OUTBUF_GTS_AND ;
    wire \AD[9]/IFF/ASYNC_FF_GSR_OR ;
    wire \AD[9]/OFF/ASYNC_FF_GSR_OR ;
    wire \Clk_SDp/KEEPER ;
    wire \AD[28]/SRNOT ;
    wire \AD[28]/IBUF ;
    wire \AD[28]/OQ ;
    wire \AD[28]/KEEPER ;
    wire \AD[28]/OUTBUF_GTS_AND ;
    wire \AD[28]/IFF/ASYNC_FF_GSR_OR ;
    wire \AD[28]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_dqm[0]/LOGIC_ZERO ;
    wire \sd_dqm[0]/KEEPER ;
    wire \AD[29]/SRNOT ;
    wire \AD[29]/IBUF ;
    wire \AD[29]/OQ ;
    wire \AD[29]/KEEPER ;
    wire \AD[29]/OUTBUF_GTS_AND ;
    wire \AD[29]/IFF/ASYNC_FF_GSR_OR ;
    wire \AD[29]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_we/SRNOT ;
    wire \sd_we/OQ ;
    wire \sd_we/KEEPER ;
    wire \sd_we/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_dqm[1]/LOGIC_ZERO ;
    wire \sd_dqm[1]/KEEPER ;
    wire \sd_add[0]/SRNOT ;
    wire \sd_add[0]/OQ ;
    wire \sd_add[0]/KEEPER ;
    wire \sd_add[0]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_dqm[2]/LOGIC_ZERO ;
    wire \sd_dqm[2]/KEEPER ;
    wire \sd_add[1]/SRNOT ;
    wire \sd_add[1]/OQ ;
    wire \sd_add[1]/KEEPER ;
    wire \sd_add[1]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_dqm[3]/LOGIC_ZERO ;
    wire \sd_dqm[3]/KEEPER ;
    wire \sd_add[2]/SRNOT ;
    wire \sd_add[2]/OQ ;
    wire \sd_add[2]/KEEPER ;
    wire \sd_add[2]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_add[3]/SRNOT ;
    wire \sd_add[3]/OQ ;
    wire \sd_add[3]/KEEPER ;
    wire \sd_add[3]/OFF/ASYNC_FF_GSR_OR ;
    wire \we_rn/IBUF ;
    wire \we_rn/KEEPER ;
    wire \sd_add[4]/SRNOT ;
    wire \sd_add[4]/OQ ;
    wire \sd_add[4]/KEEPER ;
    wire \sd_add[4]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_add[5]/SRNOT ;
    wire \sd_add[5]/OQ ;
    wire \sd_add[5]/KEEPER ;
    wire \sd_add[5]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[10]/SRNOT ;
    wire \sd_data[10]/IBUF ;
    wire \sd_data[10]/OQ ;
    wire \sd_data[10]/TQ ;
    wire \sd_data[10]/KEEPER ;
    wire \sd_data[10]/OUTBUF_GTS_AND ;
    wire \sd_data[10]/IFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[10]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[10]/TFF/ASYNC_FF_GSR_OR ;
    wire \sd_add[6]/SRNOT ;
    wire \sd_add[6]/OQ ;
    wire \sd_add[6]/KEEPER ;
    wire \sd_add[6]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[11]/SRNOT ;
    wire \sd_data[11]/IBUF ;
    wire \sd_data[11]/OQ ;
    wire \sd_data[11]/TQ ;
    wire \sd_data[11]/KEEPER ;
    wire \sd_data[11]/OUTBUF_GTS_AND ;
    wire \sd_data[11]/IFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[11]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[11]/TFF/ASYNC_FF_GSR_OR ;
    wire \sd_cs1/LOGIC_ZERO ;
    wire \sd_cs1/KEEPER ;
    wire \sd_add[7]/SRNOT ;
    wire \sd_add[7]/OQ ;
    wire \sd_add[7]/KEEPER ;
    wire \sd_add[7]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[20]/SRNOT ;
    wire \sd_data[20]/IBUF ;
    wire \sd_data[20]/OQ ;
    wire \sd_data[20]/TQ ;
    wire \sd_data[20]/KEEPER ;
    wire \sd_data[20]/OUTBUF_GTS_AND ;
    wire \sd_data[20]/IFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[20]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[20]/TFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[12]/SRNOT ;
    wire \sd_data[12]/IBUF ;
    wire \sd_data[12]/OQ ;
    wire \sd_data[12]/TQ ;
    wire \sd_data[12]/KEEPER ;
    wire \sd_data[12]/OUTBUF_GTS_AND ;
    wire \sd_data[12]/IFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[12]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[12]/TFF/ASYNC_FF_GSR_OR ;
    wire \sd_cs2/LOGIC_ZERO ;
    wire \sd_cs2/KEEPER ;
    wire \sd_add[8]/SRNOT ;
    wire \sd_add[8]/OQ ;
    wire \sd_add[8]/KEEPER ;
    wire \sd_add[8]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[13]/SRNOT ;
    wire \sd_data[13]/IBUF ;
    wire \sd_data[13]/OQ ;
    wire \sd_data[13]/TQ ;
    wire \sd_data[13]/KEEPER ;
    wire \sd_data[13]/OUTBUF_GTS_AND ;
    wire \sd_data[13]/IFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[13]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[13]/TFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[21]/SRNOT ;
    wire \sd_data[21]/IBUF ;
    wire \sd_data[21]/OQ ;
    wire \sd_data[21]/TQ ;
    wire \sd_data[21]/KEEPER ;
    wire \sd_data[21]/OUTBUF_GTS_AND ;
    wire \sd_data[21]/IFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[21]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[21]/TFF/ASYNC_FF_GSR_OR ;
    wire \sd_ba/SRNOT ;
    wire \sd_ba/OQ ;
    wire \sd_ba/KEEPER ;
    wire \sd_ba/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_add[9]/SRNOT ;
    wire \sd_add[9]/OQ ;
    wire \sd_add[9]/KEEPER ;
    wire \sd_add[9]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[30]/SRNOT ;
    wire \sd_data[30]/IBUF ;
    wire \sd_data[30]/OQ ;
    wire \sd_data[30]/TQ ;
    wire \sd_data[30]/KEEPER ;
    wire \sd_data[30]/OUTBUF_GTS_AND ;
    wire \sd_data[30]/IFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[30]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[30]/TFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[22]/SRNOT ;
    wire \sd_data[22]/IBUF ;
    wire \sd_data[22]/OQ ;
    wire \sd_data[22]/TQ ;
    wire \sd_data[22]/KEEPER ;
    wire \sd_data[22]/OUTBUF_GTS_AND ;
    wire \sd_data[22]/IFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[22]/OFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[22]/TFF/ASYNC_FF_GSR_OR ;
    wire \sd_data[14]/SRNOT ;