run_sim

这是使用VERILOG语言

/tools/cadence/verilog/tools/bin/verilog-virsim2.2.3 $XILINX/verilog/src/glbl.v tb_post_route.v sdrm_par.v ../micron/mt48lc1m16a1-8a.v -y $XILINX/verilog/src/simprims +libext+.v +pulse_e/0 +pulse_r/0 +pulse_int_e/0 +pulse_int_r/0 +transport_int_delays -l post_route.log +vpdfile+"post_route.vpd" +licq_vxl