post_route.log

这是使用VERILOG语言

Host command: /tools/cadence/verilog/tools/bin/verilog-virsim2.2.3
Command arguments:
    /tools/cheshire/denali/verify/xfndry/rtf/C_current/verilog/src/glbl.v
    tb_post_route.v
    sdrm_par.v
    ../micron/mt48lc1m16a1-8a.v
    -y /tools/cheshire/denali/verify/xfndry/rtf/C_current/verilog/src/simprims
    +libext+.v
    +pulse_e/0
    +pulse_r/0
    +pulse_int_e/0
    +pulse_int_r/0
    +transport_int_delays
    -l post_route.log
    +vpdfile+post_route.vpd
    +licq_vxl

VERILOG-XL 2.6.10 log file created Jun 29, 1999  10:52:21
VERILOG-XL 2.6.10   Jun 29, 1999  10:52:21

Copyright (c) 1995 Cadence Design Systems, Inc.  All Rights Reserved.
Unpublished -- rights reserved under the copyright laws of the United States.

Copyright (c) 1995 UNIX Systems Laboratories, Inc.  Reproduced with Permission.

THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION
AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC.  USE, DISCLOSURE, OR
REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF
CADENCE DESIGN SYSTEMS, INC.
RESTRICTED RIGHTS LEGEND

Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in
Technical Data and Computer Software clause at DFARS 252.227-7013 or
subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted
Rights at 48 CFR 52.227-19, as applicable.

                Cadence Design Systems, Inc.
                555 River Oaks Parkway
                San Jose, California  95134

For technical assistance please contact the Cadence Response Center at
1-800-CADENC2 or send email to [e-mail]

For more information on Cadence's Verilog-XL product line send email to
[e-mail]

Compiling source file "/tools/cheshire/denali/verify/xfndry/rtf/C_current/verilog/src/glbl.v"
Compiling source file "tb_post_route.v"
Compiling included source file "../src/define.v"
Continuing compilation of source file "tb_post_route.v"
Compiling included source file "string_decode_post_route.v"
Continuing compilation of source file "tb_post_route.v"
Compiling source file "sdrm_par.v"
Compiling source file "../micron/mt48lc1m16a1-8a.v"
Scanning library directory "/tools/cheshire/denali/verify/xfndry/rtf/C_current/verilog/src/simprims"
Highest level modules:
glbl
t_sdrm

   *** SDF Annotator version 2.3.3
   *** SDF Interface version 5.3.2
   ***    SDF file:  sdrm_par.sdf
   ***    Back-annotation scope:  t_sdrm.sdrmc
   ***    No configuration file specified - using default options
   ***    SDF Annotator log file:  sdf.log
   ***    No MTM selection parameter specified

   ***    No SCALE FACTORS parameter specified

   ***    No SCALE TYPE parameter specified

          Configuring for back-annotation...

          Reading SDF file and back-annotating timing data...


*** SDF back-annotation successfully completed

VCD+ 2.2.3 Copyright 1993-1998 Summit Design Inc.
                   0 0xxxx   x         x
                   2 0xxxx   x         z
                   3 01110   0         z
                   8 11110   0         z
                  16 01110   0         z

"/tools/cheshire/denali/verify/xfndry/rtf/C_current/verilog/src/simprims/X_SFF.v", 83: Timing violation in t_sdrm.sdrmc.\Act_st[2]/FFY/SYNC_FF 
    $width( posedge RST:9 ns,  : 17 ns,  13000 : 13 ns );

                  24 11110   0         z
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                 731 111101281         z
                 731 111111281         z
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at time       744 ns PRE  : Bank = ALL
at time       744 ns PRE  : Bank = ALL
                 744 101011281         z
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                 760 111111281         z
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                 792 11110   0         z
                 800 01110   0         z
                 803 01010   0         z
                 803 00010   0         z
at time       808 ns AREF : Auto Refresh
at time       808 ns AREF : Auto Refresh
                 808 10010   0         z
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at time       944 ns AREF : Auto Refresh
at time       944 ns AREF : Auto Refresh
                 944 00010   0         z
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at time      1104 ns LMR  : Load Mode Register
                            CAS Latency      = 3
                            Burst Length     = 8
                            Burst Type       = Sequential
                            Write Burst Mode = Programmed Burst Length
at time      1104 ns LMR  : Load Mode Register
                            CAS Latency      = 3
                            Burst Length     = 8
                            Burst Type       = Sequential
                            Write Burst Mode = Programmed Burst Length
                1104 00000  51         z
                1107 00110  51         z
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                1131 11110  32         z
                1131 11110   0         z
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                1139 00110   0         z
at time      1144 ns ACT  : Bank = 0 Row =    0
at time      1144 ns ACT  : Bank = 0 Row =    0
                1144 10110   0         z
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                1152 01110   0         z
                1155 011101280         z
                1160 111101280         z
                1163 110001280         z
                1164 110001280         Z
                1164 110001280         Z
                1164 110001280      4097
at time      1168 ns WRITE: Bank = 0 Row =    0, Col =   0, Data =     0, Dqm = 00
at time      1168 ns WRITE: Bank = 0 Row =    0, Col =   0, Data =  4097, Dqm = 00
                1168 010001280      4097
                1171 010001280      4099
                1171 011101280      4098
at time      1176 ns WRITE: Bank = 0 Row =    0, Col =   1, Data =     0, Dqm = 00
at time      1176 ns WRITE: Bank = 0 Row =    0, Col =   1, Data =  4098, Dqm = 00
                1176 111101280      4098
                1179 111101280      4099
at time      1184 ns WRITE: Bank = 0 Row =    0, Col =   2, Data =     0, Dqm = 00
at time      1184 ns WRITE: Bank = 0 Row =    0, Col =   2, Data =  4099, Dqm = 00
                1184 011101280      4099
                1187 011101280      4101
                1187 011101280      4100
at time      1192 ns WRITE: Bank = 0 Row =    0, Col =   3, Data =     0, Dqm = 00
at time      1192 ns WRITE: Bank = 0 Row =    0, Col =   3, Data =  4100, Dqm = 00
                1192 111101280      4100
                1195 111101280      4101
at time      1200 ns WRITE: Bank = 0 Row =    0, Col =   4, Data =     0, Dqm = 00
at time      1200 ns WRITE: Bank = 0 Row =    0, Col =   4, Data =  4101, Dqm = 00
                1200 011101280      4101
                1203 011101280      4103
                1203 011101280      4102
at time      1208 ns WRITE: Bank = 0 Row =    0, Col =   5, Data =     0, Dqm = 00
at time      1208 ns WRITE: Bank = 0 Row =    0, Col =   5, Data =  4102, Dqm = 00
                1208 111101280      4102
                1211 111101280      4103
at time      1216 ns WRITE: Bank = 0 Row =    0, Col =   6, Data =     0, Dqm = 00
at time      1216 ns WRITE: Bank = 0 Row =    0, Col =   6, Data =  4103, Dqm = 00
                1216 011101280      4103
                1219 011101280      4105
                1219 011101280      4104