sdrm_par.sdf

这是使用VERILOG语言

          (WIDTH (posedge RST) (2500:2500:2500))
        )
  )
  (CELL
    (CELLTYPE "X_OR2")
      (INSTANCE AD\[29\]\/OFF\/ASYNC_FF_GSR_OR_34)
        (DELAY
          (ABSOLUTE
            (IOPATH I0 O (0:0:0) (0:0:0))
            (IOPATH I1 O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_INV")
      (INSTANCE sd_we\/MUX_SRMUX)
        (DELAY
          (ABSOLUTE
            (PORT I (4130:4130:4130) (4130:4130:4130))
            (IOPATH I O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_TRI")
      (INSTANCE sd_we\/OUTBUF_GTS_TRI)
        (DELAY
          (ABSOLUTE
            (PORT I (2641:2641:2641) (2641:2641:2641))
            (IOPATH I O (0:0:0) (0:0:0))
            (IOPATH CTL O (0:0:0) (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_FF")
      (INSTANCE sd_we\/OFF\/ASYNC_FF)
        (DELAY
          (ABSOLUTE
            (PORT I (3852:3852:3852) (3852:3852:3852))
            (PORT CLK (404:404:404) (404:404:404))
            (IOPATH CLK O (604:604:604) (604:604:604))
            (IOPATH SET O (819:819:819) (819:819:819))
            (IOPATH RST O (0:0:0) (0:0:0))
          )
        )
        (TIMINGCHECK
          (SETUP (posedge I) (posedge CLK) (397:397:397))
          (SETUP (negedge I) (posedge CLK) (397:397:397))
          (HOLD (posedge I) (posedge CLK) (0:0:0))
          (HOLD (negedge I) (posedge CLK) (0:0:0))
          (WIDTH (posedge CLK) (1500:1500:1500))
          (WIDTH (negedge CLK) (1500:1500:1500))
          (SETUP (negedge SET) (posedge CLK) (432:432:432))
          (WIDTH (posedge SET) (2500:2500:2500))
        )
  )
  (CELL
    (CELLTYPE "X_OR2")
      (INSTANCE sd_we\/OFF\/ASYNC_FF_GSR_OR_36)
        (DELAY
          (ABSOLUTE
            (IOPATH I0 O (0:0:0) (0:0:0))
            (IOPATH I1 O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_TRI")
      (INSTANCE sd_dqm\[1\]\/OUTBUF_GTS_TRI)
        (DELAY
          (ABSOLUTE
            (PORT I (1079:1079:1079) (1079:1079:1079))
            (IOPATH I O (0:0:0) (0:0:0))
            (IOPATH CTL O (0:0:0) (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_INV")
      (INSTANCE sd_add\[0\]\/MUX_SRMUX)
        (DELAY
          (ABSOLUTE
            (PORT I (4377:4377:4377) (4377:4377:4377))
            (IOPATH I O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_TRI")
      (INSTANCE sd_add\[0\]\/OUTBUF_GTS_TRI)
        (DELAY
          (ABSOLUTE
            (PORT I (2641:2641:2641) (2641:2641:2641))
            (IOPATH I O (0:0:0) (0:0:0))
            (IOPATH CTL O (0:0:0) (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_FF")
      (INSTANCE sd_add\[0\]\/OFF\/ASYNC_FF)
        (DELAY
          (ABSOLUTE
            (PORT I (4206:4206:4206) (4206:4206:4206))
            (PORT CLK (404:404:404) (404:404:404))
            (IOPATH CLK O (604:604:604) (604:604:604))
            (IOPATH SET O (0:0:0) (0:0:0))
            (IOPATH RST O (819:819:819) (819:819:819))
          )
        )
        (TIMINGCHECK
          (SETUP (posedge I) (posedge CLK) (397:397:397))
          (SETUP (negedge I) (posedge CLK) (397:397:397))
          (HOLD (posedge I) (posedge CLK) (0:0:0))
          (HOLD (negedge I) (posedge CLK) (0:0:0))
          (WIDTH (posedge CLK) (1500:1500:1500))
          (WIDTH (negedge CLK) (1500:1500:1500))
          (SETUP (negedge RST) (posedge CLK) (432:432:432))
          (WIDTH (posedge RST) (2500:2500:2500))
        )
  )
  (CELL
    (CELLTYPE "X_OR2")
      (INSTANCE sd_add\[0\]\/OFF\/ASYNC_FF_GSR_OR_40)
        (DELAY
          (ABSOLUTE
            (IOPATH I0 O (0:0:0) (0:0:0))
            (IOPATH I1 O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_TRI")
      (INSTANCE sd_dqm\[2\]\/OUTBUF_GTS_TRI)
        (DELAY
          (ABSOLUTE
            (PORT I (1079:1079:1079) (1079:1079:1079))
            (IOPATH I O (0:0:0) (0:0:0))
            (IOPATH CTL O (0:0:0) (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_INV")
      (INSTANCE sd_add\[1\]\/MUX_SRMUX)
        (DELAY
          (ABSOLUTE
            (PORT I (4377:4377:4377) (4377:4377:4377))
            (IOPATH I O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_TRI")
      (INSTANCE sd_add\[1\]\/OUTBUF_GTS_TRI)
        (DELAY
          (ABSOLUTE
            (PORT I (2641:2641:2641) (2641:2641:2641))
            (IOPATH I O (0:0:0) (0:0:0))
            (IOPATH CTL O (0:0:0) (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_FF")
      (INSTANCE sd_add\[1\]\/OFF\/ASYNC_FF)
        (DELAY
          (ABSOLUTE
            (PORT I (4327:4327:4327) (4327:4327:4327))
            (PORT CLK (404:404:404) (404:404:404))
            (IOPATH CLK O (604:604:604) (604:604:604))
            (IOPATH SET O (0:0:0) (0:0:0))
            (IOPATH RST O (819:819:819) (819:819:819))
          )
        )
        (TIMINGCHECK
          (SETUP (posedge I) (posedge CLK) (397:397:397))
          (SETUP (negedge I) (posedge CLK) (397:397:397))
          (HOLD (posedge I) (posedge CLK) (0:0:0))
          (HOLD (negedge I) (posedge CLK) (0:0:0))
          (WIDTH (posedge CLK) (1500:1500:1500))
          (WIDTH (negedge CLK) (1500:1500:1500))
          (SETUP (negedge RST) (posedge CLK) (432:432:432))
          (WIDTH (posedge RST) (2500:2500:2500))
        )
  )
  (CELL
    (CELLTYPE "X_OR2")
      (INSTANCE sd_add\[1\]\/OFF\/ASYNC_FF_GSR_OR_44)
        (DELAY
          (ABSOLUTE
            (IOPATH I0 O (0:0:0) (0:0:0))
            (IOPATH I1 O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_CKBUF")
      (INSTANCE Clk_FBp\/BUF)
        (DELAY
          (ABSOLUTE
            (PORT I (0:0:0) (0:0:0))
            (IOPATH I O (650:650:650) (650:650:650))
          )
        )
  )
  (CELL
    (CELLTYPE "X_TRI")
      (INSTANCE sd_dqm\[3\]\/OUTBUF_GTS_TRI)
        (DELAY
          (ABSOLUTE
            (PORT I (1079:1079:1079) (1079:1079:1079))
            (IOPATH I O (0:0:0) (0:0:0))
            (IOPATH CTL O (0:0:0) (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_INV")
      (INSTANCE sd_add\[2\]\/MUX_SRMUX)
        (DELAY
          (ABSOLUTE
            (PORT I (4549:4549:4549) (4549:4549:4549))
            (IOPATH I O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_TRI")
      (INSTANCE sd_add\[2\]\/OUTBUF_GTS_TRI)
        (DELAY
          (ABSOLUTE
            (PORT I (2641:2641:2641) (2641:2641:2641))
            (IOPATH I O (0:0:0) (0:0:0))
            (IOPATH CTL O (0:0:0) (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_FF")
      (INSTANCE sd_add\[2\]\/OFF\/ASYNC_FF)
        (DELAY
          (ABSOLUTE
            (PORT I (5901:5901:5901) (5901:5901:5901))
            (PORT CLK (402:402:402) (402:402:402))
            (IOPATH CLK O (604:604:604) (604:604:604))
            (IOPATH SET O (0:0:0) (0:0:0))
            (IOPATH RST O (819:819:819) (819:819:819))
          )
        )
        (TIMINGCHECK
          (SETUP (posedge I) (posedge CLK) (397:397:397))
          (SETUP (negedge I) (posedge CLK) (397:397:397))
          (HOLD (posedge I) (posedge CLK) (0:0:0))
          (HOLD (negedge I) (posedge CLK) (0:0:0))
          (WIDTH (posedge CLK) (1500:1500:1500))
          (WIDTH (negedge CLK) (1500:1500:1500))
          (SETUP (negedge RST) (posedge CLK) (432:432:432))
          (WIDTH (posedge RST) (2500:2500:2500))
        )
  )
  (CELL
    (CELLTYPE "X_OR2")
      (INSTANCE sd_add\[2\]\/OFF\/ASYNC_FF_GSR_OR_48)
        (DELAY
          (ABSOLUTE
            (IOPATH I0 O (0:0:0) (0:0:0))
            (IOPATH I1 O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_INV")
      (INSTANCE sd_add\[3\]\/MUX_SRMUX)
        (DELAY
          (ABSOLUTE
            (PORT I (4549:4549:4549) (4549:4549:4549))
            (IOPATH I O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_TRI")
      (INSTANCE sd_add\[3\]\/OUTBUF_GTS_TRI)
        (DELAY
          (ABSOLUTE
            (PORT I (2641:2641:2641) (2641:2641:2641))
            (IOPATH I O (0:0:0) (0:0:0))
            (IOPATH CTL O (0:0:0) (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_FF")
      (INSTANCE sd_add\[3\]\/OFF\/ASYNC_FF)
        (DELAY
          (ABSOLUTE
            (PORT I (4320:4320:4320) (4320:4320:4320))
            (PORT CLK (402:402:402) (402:402:402))
            (IOPATH CLK O (604:604:604) (604:604:604))
            (IOPATH SET O (0:0:0) (0:0:0))
            (IOPATH RST O (819:819:819) (819:819:819))
          )
        )
        (TIMINGCHECK
          (SETUP (posedge I) (posedge CLK) (397:397:397))
          (SETUP (negedge I) (posedge CLK) (397:397:397))
          (HOLD (posedge I) (posedge CLK) (0:0:0))
          (HOLD (negedge I) (posedge CLK) (0:0:0))
          (WIDTH (posedge CLK) (1500:1500:1500))
          (WIDTH (negedge CLK) (1500:1500:1500))
          (SETUP (negedge RST) (posedge CLK) (432:432:432))
          (WIDTH (posedge RST) (2500:2500:2500))
        )
  )
  (CELL
    (CELLTYPE "X_OR2")
      (INSTANCE sd_add\[3\]\/OFF\/ASYNC_FF_GSR_OR_50)
        (DELAY
          (ABSOLUTE
            (IOPATH I0 O (0:0:0) (0:0:0))
            (IOPATH I1 O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_BUF")
      (INSTANCE we_rn\/INBUF)
        (DELAY
          (ABSOLUTE
            (IOPATH I O (642:642:642) (642:642:642))
          )
        )
  )
  (CELL
    (CELLTYPE "X_BUF")
      (INSTANCE we_rn\/IMUX)
        (DELAY
          (ABSOLUTE
            (IOPATH I O (126:126:126) (126:126:126))
          )
        )
  )
  (CELL
    (CELLTYPE "X_INV")
      (INSTANCE sd_add\[4\]\/MUX_SRMUX)
        (DELAY
          (ABSOLUTE
            (PORT I (4549:4549:4549) (4549:4549:4549))
            (IOPATH I O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_TRI")
      (INSTANCE sd_add\[4\]\/OUTBUF_GTS_TRI)
        (DELAY
          (ABSOLUTE
            (PORT I (2641:2641:2641) (2641:2641:2641))
            (IOPATH I O (0:0:0) (0:0:0))
            (IOPATH CTL O (0:0:0) (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_FF")
      (INSTANCE sd_add\[4\]\/OFF\/ASYNC_FF)
        (DELAY
          (ABSOLUTE
            (PORT I (4364:4364:4364) (4364:4364:4364))
            (PORT CLK (402:402:402) (402:402:402))
            (IOPATH CLK O (604:604:604) (604:604:604))
            (IOPATH SET O (0:0:0) (0:0:0))
            (IOPATH RST O (819:819:819) (819:819:819))
          )
        )
        (TIMINGCHECK
          (SETUP (posedge I) (posedge CLK) (397:397:397))
          (SETUP (negedge I) (posedge CLK) (397:397:397))
          (HOLD (posedge I) (posedge CLK) (0:0:0))
          (HOLD (negedge I) (posedge CLK) (0:0:0))
          (WIDTH (posedge CLK) (1500:1500:1500))
          (WIDTH (negedge CLK) (1500:1500:1500))
          (SETUP (negedge RST) (posedge CLK) (432:432:432))
          (WIDTH (posedge RST) (2500:2500:2500))
        )
  )
  (CELL
    (CELLTYPE "X_OR2")
      (INSTANCE sd_add\[4\]\/OFF\/ASYNC_FF_GSR_OR_53)
        (DELAY
          (ABSOLUTE
            (IOPATH I0 O (0:0:0) (0:0:0))
            (IOPATH I1 O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_INV")
      (INSTANCE sd_add\[5\]\/MUX_SRMUX)
        (DELAY
          (ABSOLUTE
            (PORT I (3616:3616:3616) (3616:3616:3616))
            (IOPATH I O (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_TRI")
      (INSTANCE sd_add\[5\]\/OUTBUF_GTS_TRI)
        (DELAY
          (ABSOLUTE
            (PORT I (2641:2641:2641) (2641:2641:2641))
            (IOPATH I O (0:0:0) (0:0:0))
            (IOPATH CTL O (0:0:0) (0:0:0) (0:0:0))
          )
        )
  )
  (CELL
    (CELLTYPE "X_FF")
      (INSTANCE sd_add\[5\]\/OFF\/ASYNC_FF)
        (DELAY
          (ABSOLUTE
            (PORT I (4682:4682:4682) (4682:4682:4682))
            (PORT CLK (448:448:448) (448:448:448))
            (IOPATH CLK O (604:604:604) (604:604:604))
            (IOPATH SET O (0:0:0) (0:0:0))
            (IOPATH RST O (819:819:819) (819:819:819))
          )
        )
        (TIMINGCHECK
          (SETUP (posedge I) (posedge CLK) (397:397:397))
          (SETUP (negedge I) (posedge CLK) (397:397:397))
          (HOLD (posedge I) (posedge CLK) (0:0:0))
          (HOLD (negedge I) (posedge CLK) (0:0:0))
          (WIDTH (posedge CLK) (1500:1500:1500))
          (WIDTH (negedge CLK) (1500:1500:1500))
          (SETUP (negedge RST) (posedge CLK) (432:432:432))
          (WIDTH (posedge RST) (2500:2500:2500))
        )
  )
  (CELL
    (CELLTYPE "X_OR2")