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📄 sdrm.edf

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💻 EDF
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(edif Synopsys_edif (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status  (written (timeStamp 1999 6 29 10 32 4)   (program "Synopsys Design Compiler" (Version "1998.08"))   (dataOrigin "Xilinx") (author "Jennifer Tran")  ) ) (external (rename xfpga_virtex_6 "xfpga_virtex-6") (edifLevel 0)  (technology (numberDefinition))  (cell (rename GND_ "GND") (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port G (direction OUTPUT)))   )  )  (cell DWLUT2_L (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port I0 (direction INPUT)) (port I1 (direction INPUT))     (port LO (direction OUTPUT))    )   )  )  (cell (rename VCC_ "VCC") (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port P (direction OUTPUT)))   )  )  (cell MUXCY_L (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port LO (direction OUTPUT)) (port S (direction INPUT))     (port DI (direction INPUT)) (port CI (direction INPUT))    )   )  )  (cell FDC (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))     (port C (direction INPUT)) (port CLR (direction INPUT))    )   )  )  (cell IOBUF_F_12 (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port O (direction OUTPUT)) (port IO (direction INOUT))     (port I (direction INPUT)) (port T (direction INPUT))    )   )  )  (cell FDP (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))     (port C (direction INPUT)) (port PRE (direction INPUT))    )   )  )  (cell FDCE (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))     (port C (direction INPUT)) (port CLR (direction INPUT))     (port CE (direction INPUT))    )   )  )  (cell FDR (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))     (port C (direction INPUT)) (port R (direction INPUT))    )   )  )  (cell OBUF_F_12 (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port O (direction OUTPUT)) (port I (direction INPUT)))   )  )  (cell IBUF (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port O (direction OUTPUT)) (port I (direction INPUT)))   )  )  (cell IBUFG (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port O (direction OUTPUT)) (port I (direction INPUT)))   )  )  (cell CLKDLL (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port CLK0 (direction OUTPUT)) (port CLK90 (direction OUTPUT))     (port CLK180 (direction OUTPUT)) (port CLK270 (direction OUTPUT))     (port CLK2X (direction OUTPUT)) (port CLKDV (direction OUTPUT))     (port LOCKED (direction OUTPUT)) (port CLKIN (direction INPUT))     (port CLKFB (direction INPUT)) (port RST (direction INPUT))    )   )  )  (cell XORCY (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port O (direction OUTPUT)) (port LI (direction INPUT))     (port CI (direction INPUT))    )   )  )  (cell FDCP (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))     (port C (direction INPUT)) (port CLR (direction INPUT))     (port PRE (direction INPUT))    )   )  )  (cell LUT2 (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port I0 (direction INPUT)) (port I1 (direction INPUT))     (port O (direction OUTPUT))    )   )  )  (cell LUT3 (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port I0 (direction INPUT)) (port I1 (direction INPUT))     (port I2 (direction INPUT)) (port O (direction OUTPUT))    )   )  )  (cell BUFG (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port O (direction OUTPUT)) (port I (direction INPUT)))   )  )  (cell LUT4 (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port I0 (direction INPUT)) (port I1 (direction INPUT))     (port I2 (direction INPUT)) (port I3 (direction INPUT))     (port O (direction OUTPUT))    )   )  )  (cell OBUF_F_16 (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port O (direction OUTPUT)) (port I (direction INPUT)))   )  )  (cell SRL16 (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))     (port A0 (direction INPUT)) (port A1 (direction INPUT))     (port A2 (direction INPUT)) (port A3 (direction INPUT))     (port CLK (direction INPUT))    )   )  )  (cell FD (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))     (port C (direction INPUT))    )   )  )  (cell FDPE (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))     (port C (direction INPUT)) (port PRE (direction INPUT))     (port CE (direction INPUT))    )   )  ) ) (library DESIGNS (edifLevel 0) (technology (numberDefinition))  (cell GND (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port G (direction OUTPUT)))   )  )  (cell VCC (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port P (direction OUTPUT)))   )  )  (cell sdrm_t_xdw_incdec_16_0 (cellType GENERIC)   (view Netlist_representation (viewType NETLIST)    (interface (port INC_DEC (direction INPUT))     (port (array (rename A_15_0_ "A[15:0]") 16) (direction INPUT))     (port (array (rename S_15_0_ "S[15:0]") 16) (direction OUTPUT))    )    (contents     (instance A_GND      (viewRef Netlist_representation       (cellRef GND_ (libraryRef xfpga_virtex_6))      )     )     (instance A_LUTI      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_CYI      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_XOR_1      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_LUT_4      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_CY_4      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_XOR_8      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_LUT_11      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_CY_14      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_LUT_2      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_CY_2      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_LUT_3      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_CY_3      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_XOR_6      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_CY_13      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_XOR_11      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_XOR_7      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_XOR_10      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_CY_12      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_LUT_5      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_XOR_9      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_VCC      (viewRef Netlist_representation       (cellRef VCC_ (libraryRef xfpga_virtex_6))      )     )     (instance A_XORI      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_XOR_2      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_CY_5      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_LUT_10      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_CY_15      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_LUT_7      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_CY_7      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_XOR_15      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_XOR_5      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_CY_10      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_LUT_12      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_LUT_15      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_LUT_1      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_CY_1      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_LUT_9      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_XOR_12      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_CY_9      (viewRef Netlist_representation       (cellRef MUXCY_L (libraryRef xfpga_virtex_6))      )     )     (instance A_XOR_4      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )     )     (instance A_LUT_8      (viewRef Netlist_representation       (cellRef DWLUT2_L (libraryRef xfpga_virtex_6))      )      (property INIT (string "6")) (property EQN (string "(I0 @ I1)"))     )     (instance A_XOR_13      (viewRef Netlist_representation       (cellRef XORCY (libraryRef xfpga_virtex_6))      )

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