run_par

这是使用VERILOG语言

#!/bin/csh -f

set DESIGN = "sdrm"
set PART = "xcv300bg432"
set LEVEL = "4"
set FAMILY = "virtex"

if ($XILINX == "") then
  echo "XILINX variable must be set to Xilinx s/w"
  exit 1 
endif

/bin/rm *.ngd *.ncd *.v *.sdf

echo "ngdbuild -p $PART ${DESIGN} -uc ${DESIGN}"
ngdbuild -p $PART ${DESIGN} -uc ${DESIGN}

echo "map -pr b -p $PART ${DESIGN}"  # -pr b pushes registers in IOBs
map -pr b -p $PART ${DESIGN}  # -pr b pushes registers in IOBs

echo "par -w -ol $LEVEL ${DESIGN} ${DESIGN}_par ${DESIGN}.pc"f 
par -w -ol $LEVEL ${DESIGN} ${DESIGN}_par ${DESIGN}.pcf 

#run timing analyzer
echo "trce -v -u ${DESIGN}_par ${DESIGN}.pcf"
trce -v -u ${DESIGN}_par ${DESIGN}.pcf

#create bitstream
echo "bitgen -wb ${DESIGN}_par.ncd"
bitgen -wb ${DESIGN}_par.ncd

#create backannotated netlist for simulation
echo "ngdanno ${DESIGN}_par"
ngdanno ${DESIGN}_par
echo "ngd2ver -w ${DESIGN}_par ${DESIGN}_par.v"
ngd2ver -w ${DESIGN}_par ${DESIGN}_par.v