sdrm.scr

这是使用VERILOG语言

include "setup.scr"

/*********************/
/* Read design files */
/*********************/

read -f verilog { \
	"../src/define.v"  \
	"../src/rcd_cntr.v"  \
	"../src/brst_cntr.v" \
	"../src/cslt_cntr.v" \
	"../src/ref_cntr.v" \
	"../src/ki_cntr.v" \
	"../src/sdrmc_state.v" \
	"../src/sys_int.v" \
	"../src/sdrm_t.v" \
	"../src/sdrm.v" \
}


/*************************/
/* Compile state machine */
/*************************/
current_design= sdrmc_state
create_clock Clk -period 10 -waveform {0 5}
set_critical_range 20.0 current_design
report_fsm
compile -map high
report_fsm

check_design > "sdrmc_state.chk"
report_timing -path full -max_paths 100 -nosplit > "sdrmc_state.time"
report_area > "sdrmc_state.area"
write -hier -f db -o  "sdrmc_state.db" 
/* set_dont_touch current_design */

/**********************/
/* Compile controller */
/**********************/
current_design = sdrm_t
ungroup -all

/* clock constraints */
create_clock Clk_i -period 10 -waveform {0 5}
dont_touch_network Clk_i
set_driving_cell -none Clk_i
set_drive 0.0 Clk_i

create_clock Clk_j -period 20 -waveform {0 10}
dont_touch_network Clk_j
set_driving_cell -none Clk_j
set_drive 0.0 Clk_j

/* output constraints */
set_output_delay 7.5 {sd_add_o sd_ras_o sd_cas_o sd_we_o sd_ba_o sd_doe_n} -clock Clk_i

set_critical_range 20.0 current_design

set_dont_touch find(net, sd_doe_n[*])
check_design > "sdrm_t.chk"
compile -map_effort high
report_timing -path full -max_paths 100 -nosplit > "sdrm_t.time"
report_area > "sdrm_t.area"
write -hier -f db -o  "sdrm_t.db"  
/* set_dont_touch current_design */


/**************************************************************/
/* compile top-level design (controller & processor interface */
/**************************************************************/
current_design = sdrm

create_clock Clkp -period 20 -waveform {0 10}
set_false_path -from {Reset }

set_output_delay 7.5 {sd_add* sd_ras sd_cas sd_we sd_ba } -clock Clkp

set_dont_touch find(net, we_rn_i_buf[*])
set_dont_touch find(net, adsn_i_buf[*])
set_dont_touch find(net, AD_tri[*])

set_dont_touch find(net, sd_data_t*)
set_dont_touch find(net, sd_doe_n[*])
set_dont_touch find(net, sd_doe_n[*])
set_dont_touch find(net, sd_cs1)
set_dont_touch find(net, sd_cs2)
set_dont_touch find(net, sd_dqm[*])

set_dont_touch {ibufg0 ibufg1 dll0 dll1 obuf0 bufg0 }
set_dont_touch {iod0 iod1 iod2 iod3 iod4 iod5}
set_dont_touch {iod6 iod7 iod8 iod9}
set_dont_touch {iod10 iod11 iod12 iod13 iod14}
set_dont_touch {iod15 iod16 iod17 iod18 iod19}
set_dont_touch {iod20 iod21 iod22 iod23 iod24}
set_dont_touch {iod25 iod26 iod27 iod28 iod29}
set_dont_touch {iod30 iod31 sdb sdr sdc sdw}
set_dont_touch {sda0 sda1 sda2 sda3 sda4 sda5}
set_dont_touch {sda6 sda7 sda8 sda9 sda10}
set_dont_touch {dqm0 dqm1 dqm2 dqm3 sdcke sdcs1 sdcs2 rdy ads_b wern_b}


check_design > "sdrm.chk"
compile -boundary_optimization -map_effort high
report_area -nosplit > "sdrm.area"  
report_cell -nosplit > "sdrm.cell"  
report_timing -path full -max_paths 100 -nosplit > "sdrm.time"

/**********************/
/* Write output files */
/**********************/
write -hierarchy -o  "sdrm.db"
write -hier -format edif -output sdrm.edf 
write -hier -f verilog -o  "sdrm_gate_level.v" 

exit