setup.scr

这是使用VERILOG语言

/* =================================================== */
/* Template .synopsys_dc.setup file for Xilinx designs */
/*       For use with Synopsys FPGA Compiler.          */
/* =================================================== */

/* ================================================= */
/* The Synopsys search path should be set to point   */
/* to the directories that contain the various       */  
/* synthesis libraries used by FPGA Compiler during  */
/* synthesis.                                        */
/* ================================================= */

XilinxInstall = get_unix_variable(XILINX); 
SynopsysInstall = get_unix_variable(SYNOPSYS);

search_path = { .       \
        XilinxInstall + /synopsys/libraries/syn \
        SynopsysInstall + /libraries/syn }

                /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
                /* Ensure that your UNIX environment */
                /* includes the two environment var- */
                /* iables: $XILINX (points to the    */
                /* Xilinx installation directory) and*/
                /* $SYNOPSYS (points to the Synopsys */
                /* installation directory.)          */  
                /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */

/* ================================================= */
/* Define a work library in the current project dir  */
/* to hold temporary files and keep the project area */
/* uncluttered. Note: You must create a subdirectory */
/* in your project directory called WORK.            */  
/* ================================================= */
 

   define_design_lib WORK -path ./WORK
   define_design_lib unisim -path ../lib/unisims

/* ================================================= */
/* Declare the use of the Xilinx DesignWare library  */
/* for use during synthesis. The following command   */
/* shows the Virtex DesignWare library selected.     */
/* Note that this pointer must be set to point to    */
/* the target architecture's DesignWare library.     */  
/* ================================================= */

define_design_lib xdw_virtex -path XilinxInstall + /synopsys/libraries/dw/lib/virtex

link_library = {"*" "xfpga_virtex-6.db"}
target_library = {xfpga_virtex-6.db}
symbol_library = {virtex.sdb}
synthetic_library = {xdw_virtex.sldb standard.sldb}

bus_extraction_style = "%s[%d:%d]"
bus_naming_style = "%s[%d]"
bus_dimension_separator_style = "[]"

/*
hdlin_replace_synthetic = "true"
hdlin_ff_always_async_set_reset = "FALSE"
hdlin_ff_always_sync_set_reset  = "TRUE"
*/
edifin_lib_logic_1_symbol = "VCC"
edifin_lib_logic_0_symbol = "GND"
edifout_ground_name = "GND"
edifout_ground_pin_name = "G"
edifout_power_name = "VCC"
edifout_power_pin_name = "P"
edifout_netlist_only = "true"
edifout_no_array = "false"
edifout_power_and_ground_representation = "cell"
edifout_write_properties_list = { \
"INIT_00" "INIT_01" "INIT_02" "INIT_03" "INIT_04"  "INIT_05" \
"INIT_06" "INIT_07" "INIT_08" "INIT_09" "INIT_0A" "INIT_0B"  \
"INIT_0C" "INIT_0D" "INIT_0E" "INIT_0F" "INIT" \
"IOB" "EQN" "lut_function" "LOC" "RLOC" "RLOC_ORIGIN" \
"DUTY_CYCLE_CORRECTION" "CLKDV_DIVIDE" "FACTORY_JF" "CLK2X_FB" \
"HIGH_FREQUENCY" "STARTUP_WAIT" "S" "X" "K"\
}

hdlin_translate_off_skip_text = true