func_sim.cfg

这是使用VERILOG语言

# Virsim Configuration File
version "2.2.0"

# Files Open:
#   Designator  Sources  Filename
#   ----------  -------  --------
#       V1         y     /home/efc3_d/virtexe/proj/work/sdrm_1.13/func_sim/func_sim.vpd

define exprgroup AutoExprGroup0;

define linkwindow A
	time 8000 "1 ps",
	exprgroup "AutoExprGroup0";

define group read
	add " " "  " blank 1 ,
	add " " "  " blank 1 ,
	add " " "  " blank 1 ,
	add " " "  " blank 1 ,
	add " " "  " blank 1 ,
	add " " "  " blank 1 ,
	add " " "  " blank 1 ,
	add " " "  " blank 1 ;

define group write
	add "V1" "t_sdrm.sdrmc.Clkp" strength 1 ,
	add "V1" "t_sdrm.string_proc_cmd[200:1]" ascii 1 ,
	add "V1" "t_sdrm.sdrmc.AD[31:0]" hex 1 ,
	add "V1" "t_sdrm.string_ctrl_state[200:1]" ascii 1 ,
	add "V1" "t_sdrm.sdrmc.Clk_SDp" strength 1 ,
	add "V1" "t_sdrm.string_sdrm_cmd[200:1]" ascii 1 ,
	add "V1" "t_sdrm.sdrmc.sd_data[31:0]" hex 1 ,
	add "V1" "t_sdrm.sdrmc.sd_add[10:0]" hex 1 ;

define hierarchy
	xposition 476,
	yposition -10,
	width 566,
	height 738,
	designator "V1",
	layout "default",
	topscope "t_sdrm",
	pane1 199,
	focusscope "t_sdrm.sdrmc.sdrm_t",
	pane2 268,
	locate "scopes",
	find "current",
	findtext "*",
	pane3 282,
	signals on,
	ports on,
	filtertext "*pre_ad_tri*",
	signalscope "t_sdrm.sdrmc.sdrm_t";

define wave
	xposition 28,
	yposition -15,
	width 1131,
	height 626,
	linkwindow A,
	displayinfo 5830 "1 ps" tpp 2915 0,
	group "write",
	pane1 141,
	pane2 94;