cdu60.vhd

电子钏的硬件描述语言设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cdu60  is
port (  clk1,clk2,ss :in std_logic;
      co : out std_logic;
      m :out std_logic_vector (7 downto 0));
end cdu60 ;
architecture aa of cdu60 is
 signal out1,out2 :integer range 0 to 9;
 signal out3,out4 :std_logic_vector (3 downto 0);
 signal clk,cay:std_logic;
begin
co<= cay when ss='0' else '0';
clk<=clk1 when ss='0' else clk2;
process(clk)
begin
if clk'event and clk='1' then
--if en='1' then

--if clr='1' then
--out1<=0;
--out2<=0;
if (out2=5) and (out1=9)  then
out1<=0;
out2<=0;
cay<='1';
else
out1<=out1+1;
cay<='0';
if out1=9 and out2/=5 then
out1<=0;
out2<=out2+1;
cay<='0';

end if;
end if;
--end if;
--end if;
end if;
out3<= conv_std_logic_vector(out1,4);
out4<= conv_std_logic_vector(out2,4);

m<=out4 & out3;
end process;
end aa;