cdu60s.vhd

来自「电子钏的硬件描述语言设计」· VHDL 代码 · 共 45 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cdu60s  is
port (  clk1,clr :in std_logic;
      co : out std_logic;
      m :out std_logic_vector (7 downto 0));
end cdu60s ;

architecture aa of cdu60s is
 signal out1,out2 :integer range 0 to 9;
 signal out3,out4 :std_logic_vector (3 downto 0);
 signal clk:std_logic;
begin
process(clk1)
begin
if clr='1' then out1<=0; out2<=0;
elsif clk1'event and clk1='1' then
if (out2=5) and (out1=9) then
out1<=0;
out2<=0;
co<='1';
else
out1<=out1+1;
co<='0';
if out1=9 and out2/=5 then
out1<=0;
out2<=out2+1;
co<='0';

end if;
end if;
end if;

out3<= conv_std_logic_vector(out1,4);
out4<= conv_std_logic_vector(out2,4);

m<=out4 & out3;
end process;
end aa;