leddrv.vhd

电子钏的硬件描述语言设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY leddrv IS
PORT
(
 ms10       :IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
 sec        :IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
 min        :IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
 en         :IN STD_LOGIC;
 clk		:IN STD_LOGIC;
 Lseg       :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
 Lcs        :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END leddrv;

ARCHITECTURE behave OF leddrv IS
SIGNAL v:STD_LOGIC_VECTOR(3 DOWNTO 0); --取得要的单个七段管的实际数值
BEGIN
PROCESS(clk)
VARIABLE n:INTEGER RANGE 0 TO 9;
BEGIN
IF en='0' THEN Lseg<="00000000"; Lcs<="00000000";
 ELSIF rising_edge(clk) THEN --时钟上升沿后
   n:=n+1;
   if n>8 then n:=1;end if;
     if     n=1 then v<=ms10(3 downto 0);Lcs<="00000001";
      elsif n=2 then v<=ms10(7 downto 4);Lcs<="00000010";
      elsif n=3 then v<="1110";          Lcs<="00000100";
      elsif n=4 then v<=sec(3 downto 0); Lcs<="00001000";
      elsif n=5 then v<=sec(7 downto 4); Lcs<="00010000";
      elsif n=6 then v<="1111";          Lcs<="00100000";
      elsif n=7 then v<=min(3 downto 0); Lcs<="01000000";
      elsif n=8 then v<=min(7 downto 4); Lcs<="10000000";
      else Lcs<="00000000";
   end if;
   if     v="0000" then Lseg<="11111100";
    elsif v="0001" then Lseg<="01100000";
    elsif v="0010" then Lseg<="11011010";
    elsif v="0011" then Lseg<="11110010";
    elsif v="0100" then Lseg<="01100110";
    elsif v="0101" then Lseg<="10110110";
    elsif v="0110" then Lseg<="10111110";
    elsif v="0111" then Lseg<="11100000";
    elsif v="1000" then Lseg<="11111110";
    elsif v="1001" then Lseg<="11110110";
    else Lseg<="00000001";--不为0~9,显示成小数点
   end if;
END IF;
END PROCESS;
END behave;