📄 clkgdf.rpt
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Total dedicated input pins used: 3/6 ( 50%)
Total I/O pins used: 20/53 ( 37%)
Total logic cells used: 134/576 ( 23%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.35/4 ( 83%)
Total fan-in: 449/2304 ( 19%)
Total input pins required: 6
Total input I/O cell registers required: 0
Total output pins required: 17
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 134
Total flipflops required: 63
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 17/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 4 1 4 1 1 2 1 1 1 1 6 1 0 3 1 0 0 0 0 0 0 3 0 8 1 40/0
B: 1 4 1 0 1 4 4 1 1 1 0 8 0 0 0 4 1 0 1 8 0 0 7 0 0 47/0
C: 1 1 1 8 7 1 1 3 1 5 0 1 0 0 0 0 0 8 0 0 8 0 0 0 1 47/0
Total: 6 6 6 9 9 7 6 5 3 7 6 10 0 3 1 4 1 8 1 8 8 3 7 8 2 134/0
Device-Specific Information: d:\clkgdf\clkgdf.rpt
clkgdf
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
43 - - - -- INPUT G 0 0 0 1 cp1
1 - - - -- INPUT G 0 0 0 1 cp2
28 - - C -- INPUT 0 0 0 1 k1
29 - - C -- INPUT 0 0 0 1 k2
30 - - C -- INPUT 0 0 0 9 k3
42 - - - -- INPUT 0 0 0 0 k16
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\clkgdf\clkgdf.rpt
clkgdf
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
27 - - C -- OUTPUT 0 1 0 0 bee
3 - - - 12 OUTPUT 0 1 0 0 ms1
72 - - A -- OUTPUT 0 1 0 0 ms2
73 - - A -- OUTPUT 0 1 0 0 ms3
78 - - - 24 OUTPUT 0 1 0 0 ms4
79 - - - 24 OUTPUT 0 1 0 0 ms5
80 - - - 23 OUTPUT 0 1 0 0 ms6
81 - - - 22 OUTPUT 0 1 0 0 ms7
83 - - - 13 OUTPUT 0 1 0 0 ms8
5 - - - 05 OUTPUT 0 1 0 0 seg0
6 - - - 04 OUTPUT 0 1 0 0 seg1
7 - - - 03 OUTPUT 0 1 0 0 seg2
8 - - - 03 OUTPUT 0 1 0 0 seg3
9 - - - 02 OUTPUT 0 1 0 0 seg4
10 - - - 01 OUTPUT 0 1 0 0 seg5
11 - - - 01 OUTPUT 0 1 0 0 seg6
16 - - A -- OUTPUT 0 1 0 0 seg7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\clkgdf\clkgdf.rpt
clkgdf
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - B 19 OR2 ! 0 2 0 3 |CDU24:4|LPM_ADD_SUB:150|addcore:adder|:55
- 5 - B 22 AND2 0 2 0 1 |CDU24:4|LPM_ADD_SUB:181|addcore:adder|:55
- 4 - B 22 AND2 0 3 0 1 |CDU24:4|LPM_ADD_SUB:181|addcore:adder|:59
- 3 - B 22 DFFE 0 4 0 2 |CDU24:4|out23 (|CDU24:4|:14)
- 1 - B 22 DFFE 0 4 0 3 |CDU24:4|out22 (|CDU24:4|:15)
- 2 - B 22 DFFE 0 4 0 4 |CDU24:4|out21 (|CDU24:4|:16)
- 1 - B 18 DFFE 0 3 0 5 |CDU24:4|out20 (|CDU24:4|:17)
- 3 - B 19 DFFE 0 4 0 3 |CDU24:4|out13 (|CDU24:4|:18)
- 4 - B 19 DFFE 0 3 0 4 |CDU24:4|out12 (|CDU24:4|:19)
- 7 - B 19 DFFE 0 3 0 3 |CDU24:4|out11 (|CDU24:4|:20)
- 1 - B 16 DFFE 0 1 0 4 |CDU24:4|out10 (|CDU24:4|:21)
- 6 - B 22 OR2 s 0 4 0 1 |CDU24:4|~114~1
- 2 - B 19 OR2 ! 0 4 0 5 |CDU24:4|:114
- 1 - B 19 OR2 ! 0 4 0 5 |CDU24:4|:160
- 6 - B 19 AND2 s 0 2 0 3 |CDU24:4|~268~1
- 2 - C 10 OR2 0 4 0 8 |CDU24:4|:493
- 3 - B 02 AND2 0 2 0 2 |CDU60:3|LPM_ADD_SUB:157|addcore:adder|:55
- 6 - B 12 AND2 0 2 0 1 |CDU60:3|LPM_ADD_SUB:199|addcore:adder|:55
- 7 - B 12 AND2 0 3 0 1 |CDU60:3|LPM_ADD_SUB:199|addcore:adder|:59
- 3 - B 12 DFFE 0 4 0 3 |CDU60:3|out23 (|CDU60:3|:14)
- 2 - B 12 DFFE 0 4 0 5 |CDU60:3|out22 (|CDU60:3|:15)
- 4 - B 12 DFFE 0 4 0 5 |CDU60:3|out21 (|CDU60:3|:16)
- 1 - B 12 DFFE 0 3 0 7 |CDU60:3|out20 (|CDU60:3|:17)
- 1 - B 02 DFFE 0 4 0 4 |CDU60:3|out13 (|CDU60:3|:18)
- 2 - B 02 DFFE 0 3 0 4 |CDU60:3|out12 (|CDU60:3|:19)
- 1 - B 09 DFFE 0 3 0 4 |CDU60:3|out11 (|CDU60:3|:20)
- 1 - B 01 DFFE 0 1 0 6 |CDU60:3|out10 (|CDU60:3|:21)
- 5 - B 12 DFFE 0 3 0 1 |CDU60:3|cay (|CDU60:3|:22)
- 2 - B 03 AND2 s 0 4 0 8 |CDU60:3|~115~1
- 8 - B 12 AND2 0 4 0 5 |CDU60:3|:176
- 4 - B 02 AND2 s 0 1 0 1 |CDU60:3|~300~1
- 1 - C 10 OR2 0 3 0 9 |CDU60:3|:519
- 2 - C 06 AND2 0 2 0 1 |CDU60S:2|LPM_ADD_SUB:182|addcore:adder|:55
- 6 - C 05 AND2 0 2 0 1 |CDU60S:2|LPM_ADD_SUB:224|addcore:adder|:55
- 7 - C 05 AND2 0 3 0 1 |CDU60S:2|LPM_ADD_SUB:224|addcore:adder|:59
- 3 - C 10 DFFE 0 4 0 1 |CDU60S:2|:3
- 6 - C 04 DFFE 1 4 0 3 |CDU60S:2|out13 (|CDU60S:2|:13)
- 7 - C 04 DFFE 1 4 0 4 |CDU60S:2|out12 (|CDU60S:2|:14)
- 1 - C 01 DFFE 1 3 0 5 |CDU60S:2|out11 (|CDU60S:2|:15)
- 1 - C 09 DFFE 1 1 0 6 |CDU60S:2|out10 (|CDU60S:2|:16)
- 2 - C 05 DFFE 1 4 0 3 |CDU60S:2|out23 (|CDU60S:2|:17)
- 5 - C 05 DFFE 1 4 0 5 |CDU60S:2|out22 (|CDU60S:2|:18)
- 2 - C 08 DFFE 1 4 0 5 |CDU60S:2|out21 (|CDU60S:2|:19)
- 1 - C 12 DFFE 1 3 0 7 |CDU60S:2|out20 (|CDU60S:2|:20)
- 4 - C 04 OR2 s ! 0 4 0 6 |CDU60S:2|~140~1
- 1 - C 02 OR2 ! 0 4 0 5 |CDU60S:2|:201
- 2 - C 03 AND2 s 0 1 0 3 |CDU60S:2|~319~1
- 8 - C 20 OR2 ! 0 2 0 3 |CONTROL:43|LPM_ADD_SUB:193|addcore:adder|:79
- 7 - C 20 OR2 ! 0 3 0 2 |CONTROL:43|LPM_ADD_SUB:193|addcore:adder|:87
- 1 - C 20 OR2 ! 0 2 0 3 |CONTROL:43|LPM_ADD_SUB:193|addcore:adder|:91
- 4 - C 17 OR2 ! 0 3 0 5 |CONTROL:43|LPM_ADD_SUB:193|addcore:adder|:99
- 2 - C 17 DFFE + 0 4 0 13 |CONTROL:43|:24
- 4 - C 10 DFFE 1 1 0 2 |CONTROL:43|:27
- 5 - C 10 DFFE 1 1 0 1 |CONTROL:43|:29
- 5 - C 17 DFFE + 0 3 0 2 |CONTROL:43|count9 (|CONTROL:43|:31)
- 6 - C 17 DFFE + 0 3 0 3 |CONTROL:43|count8 (|CONTROL:43|:32)
- 7 - C 17 DFFE + 0 2 0 4 |CONTROL:43|count7 (|CONTROL:43|:33)
- 8 - C 17 DFFE + 0 3 0 1 |CONTROL:43|count6 (|CONTROL:43|:34)
- 3 - C 17 DFFE + 0 2 0 2 |CONTROL:43|count5 (|CONTROL:43|:35)
- 6 - C 20 DFFE + 0 2 0 1 |CONTROL:43|count4 (|CONTROL:43|:36)
- 5 - C 20 DFFE + 0 3 0 1 |CONTROL:43|count3 (|CONTROL:43|:37)
- 4 - C 20 DFFE + 0 2 0 2 |CONTROL:43|count2 (|CONTROL:43|:38)
- 3 - C 20 DFFE + 0 2 0 1 |CONTROL:43|count1 (|CONTROL:43|:39)
- 2 - C 20 DFFE + 0 0 0 2 |CONTROL:43|count0 (|CONTROL:43|:40)
- 1 - C 17 OR2 0 4 0 8 |CONTROL:43|:95
- 2 - B 08 AND2 s 0 4 0 1 |CONTROL:43|~532~1
- 3 - C 05 AND2 s 0 4 0 1 |CONTROL:43|~532~2
- 1 - C 05 OR2 0 4 1 0 |CONTROL:43|:532
- 4 - C 05 AND2 s 1 2 0 1 |CONTROL:43|~533~1
- 1 - B 10 AND2 s 0 4 0 1 |CONTROL:43|~533~2
- 5 - C 04 AND2 s 1 3 0 1 |CONTROL:43|~534~1
- 3 - C 04 AND2 s 0 4 0 1 |CONTROL:43|~534~2
- 3 - B 05 AND2 s 0 4 0 1 |CONTROL:43|~534~3
- 4 - C 24 SOFT s ! 1 0 0 1 k3~1
- 1 - A 07 DFFE + 0 4 1 0 |LEDDRV:19|:27
- 1 - A 01 DFFE + 0 4 1 0 |LEDDRV:19|:29
- 3 - A 01 DFFE + 0 4 1 0 |LEDDRV:19|:31
- 2 - A 01 DFFE + 0 4 1 0 |LEDDRV:19|:33
- 1 - A 03 DFFE + 0 4 1 0 |LEDDRV:19|:35
- 2 - A 03 DFFE + 0 4 1 0 |LEDDRV:19|:37
- 3 - A 03 DFFE + 0 4 1 0 |LEDDRV:19|:39
- 1 - A 05 DFFE + 0 4 1 0 |LEDDRV:19|:41
- 1 - A 13 DFFE + 0 4 1 0 |LEDDRV:19|:43
- 1 - A 21 DFFE + 0 4 1 0 |LEDDRV:19|:45
- 1 - A 23 DFFE + 0 4 1 0 |LEDDRV:19|:47
- 3 - A 23 DFFE + 0 4 1 0 |LEDDRV:19|:49
- 2 - A 23 DFFE + 0 4 1 0 |LEDDRV:19|:51
- 1 - A 24 DFFE + 0 4 1 0 |LEDDRV:19|:53
- 2 - A 14 DFFE + 0 4 1 0 |LEDDRV:19|:55
- 1 - A 11 DFFE + 0 4 1 0 |LEDDRV:19|:57
- 2 - C 04 DFFE + 0 3 0 13 |LEDDRV:19|v3 (|LEDDRV:19|:59)
- 1 - C 04 DFFE + 0 3 0 13 |LEDDRV:19|v2 (|LEDDRV:19|:60)
- 1 - C 08 DFFE + 0 3 0 13 |LEDDRV:19|v1 (|LEDDRV:19|:61)
- 2 - A 11 DFFE + 0 3 0 11 |LEDDRV:19|v0 (|LEDDRV:19|:62)
- 5 - A 21 DFFE + 0 3 0 19 |LEDDRV:19|n3~296 (|LEDDRV:19|:70)
- 4 - A 13 DFFE + 0 3 0 18 |LEDDRV:19|n2~296 (|LEDDRV:19|:71)
- 4 - A 21 DFFE + 0 2 0 19 |LEDDRV:19|n1~296 (|LEDDRV:19|:72)
- 3 - A 13 DFFE + 0 3 0 19 |LEDDRV:19|n0~296 (|LEDDRV:19|:73)
- 4 - A 11 AND2 0 4 0 4 |LEDDRV:19|:374
- 3 - A 11 AND2 0 4 0 4 |LEDDRV:19|:379
- 5 - A 11 AND2 0 4 0 4 |LEDDRV:19|:384
- 3 - A 09 AND2 0 4 0 4 |LEDDRV:19|:389
- 3 - A 02 AND2 0 4 0 4 |LEDDRV:19|:394
- 5 - A 23 AND2 0 4 0 4 |LEDDRV:19|:399
- 4 - A 23 AND2 0 4 0 4 |LEDDRV:19|:404
- 8 - A 23 OR2 ! 0 4 0 4 |LEDDRV:19|:409
- 3 - B 15 OR2 0 3 0 1 |LEDDRV:19|:775
- 2 - B 15 OR2 0 4 0 1 |LEDDRV:19|:787
- 1 - B 07 OR2 0 3 0 1 |LEDDRV:19|:793
- 6 - B 07 OR2 0 4 0 1 |LEDDRV:19|:805
- 5 - C 07 OR2 0 3 0 1 |LEDDRV:19|:811
- 4 - B 15 OR2 0 3 0 1 |LEDDRV:19|:823
- 1 - B 15 OR2 0 4 0 1 |LEDDRV:19|:829
- 2 - B 07 OR2 0 3 0 1 |LEDDRV:19|:832
- 4 - B 07 OR2 0 4 0 1 |LEDDRV:19|:838
- 8 - C 04 OR2 0 3 0 1 |LEDDRV:19|:841
- 7 - B 22 OR2 0 3 0 1 |LEDDRV:19|:850
- 5 - B 19 OR2 0 4 0 1 |LEDDRV:19|:856
- 1 - B 06 OR2 0 3 0 1 |LEDDRV:19|:859
- 4 - B 06 OR2 0 4 0 1 |LEDDRV:19|:865
- 3 - C 08 OR2 0 3 0 1 |LEDDRV:19|:868
- 7 - A 23 OR2 0 3 0 1 |LEDDRV:19|:877
- 6 - A 23 OR2 0 4 0 1 |LEDDRV:19|:883
- 2 - B 06 OR2 0 3 0 1 |LEDDRV:19|:886
- 3 - B 06 OR2 0 3 0 1 |LEDDRV:19|:889
- 6 - A 11 OR2 0 4 0 1 |LEDDRV:19|:895
- 1 - A 06 OR2 ! 0 4 0 2 |LEDDRV:19|:1139
- 5 - A 10 AND2 0 4 0 2 |LEDDRV:19|:1157
- 2 - A 04 OR2 ! 0 4 0 2 |LEDDRV:19|:1416
- 3 - A 06 AND2 s 0 3 0 2 |LEDDRV:19|~1434~1
- 4 - A 01 OR2 0 4 0 1 |LEDDRV:19|:1469
- 4 - A 03 OR2 0 4 0 1 |LEDDRV:19|:1530
- 1 - A 08 OR2 s 0 4 0 2 |LEDDRV:19|~1574~1
- 2 - A 12 OR2 s 0 3 0 4 |LEDDRV:19|~1679~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\clkgdf\clkgdf.rpt
clkgdf
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 13/ 48( 27%) 4/ 48( 8%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 8/ 96( 8%) 14/ 48( 29%) 13/ 48( 27%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 5/ 96( 5%) 22/ 48( 45%) 2/ 48( 4%) 3/16( 18%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
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