clk_div2n.vhd

这是用VHDL 语言编写的参数可以直接设置的2n倍时钟分频器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY clk_div2n IS
GENERIC(clk_divide : INTEGER :=38--倍分频数,实际值为N
		 );

PORT(
 	CLKin :IN STD_LOGIC;
    CLKout :OUT STD_LOGIC   
);
END clk_div2n;

ARCHITECTURE bhv OF clk_div2n IS
SIGNAL   counter: integer range 0 to clk_divide-1 :=0;
SIGNAL   Clk: std_logic;
BEGIN
 PROCESS(CLKin)
 BEGIN
   IF rising_edge(CLKin) THEN 
    IF counter=clk_divide-1 THEN counter<=0;
    CLK<=NOT CLK;
   ELSE
     counter<= counter+1;
   END IF;
  END IF;
 END PROCESS;
CLKout<=CLK;
END bhv;