coregen.cgp

verilog实现16*16位乘法器

SET flowvendor = Other
SET vhdlsim = False
SET verilogsim = True
SET workingdirectory = D:\My_Designs\example\class7\multiplier\coregen\tmp
SET speedgrade = -5
SET simulationfiles = Behavioral
SET asysymbol = False
SET addpads = False
# SET outputdirectory = D:\My_Designs\example\class7\multiplier\coregen\
SET device = xc3s200
# SET projectname = coregen
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = tq144
SET createndf = False
SET designentry = Verilog
SET devicefamily = spartan3
SET formalverification = False
SET removerpms = False