multi_16x16.xco

verilog实现16*16位乘法器

# BEGIN Project Options
SET flowvendor = Other
SET vhdlsim = False
SET verilogsim = True
SET workingdirectory = D:\My_Designs\example\class7\multiplier\coregen\tmp
SET speedgrade = -5
SET simulationfiles = Behavioral
SET asysymbol = False
SET addpads = False
# SET outputdirectory = D:\My_Designs\example\class7\multiplier\coregen\
SET device = xc3s200
# SET projectname = coregen
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = tq144
SET createndf = False
SET designentry = Verilog
SET devicefamily = spartan3
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Multiplier family Xilinx,_Inc. 7.0
# END Select
# BEGIN Parameters
CSET pipelined=Minimum
CSET create_rpm=true
CSET output_width=32
CSET port_a_input=Parallel
CSET asynchronous_clear=true
CSET synchronous_clear=false
CSET memory_type=Distributed_Memory
CSET clock_enable=false
CSET port_a_data=Signed
CSET clk_cycles_per_input=1
CSET load_done_output=false
CSET ce_overrides=CE_Overrides_SCLR
CSET nd=false
CSET register_input=true
CSET port_b_width=16
CSET port_b_data=Signed
CSET port_b_constant_value=1
CSET component_name=multi_16x16
CSET port_a_width=16
CSET style=Rectangular_Shape
CSET output_hold_register=false
CSET multiplier_construction=Use_LUTs
CSET multiplier_type=Parallel
CSET output_options=Registered
CSET port_b_constant=false
CSET reload_options=Stop_During_Reload
CSET rfd=false
CSET virtex2_multiplier_optimization=Area
CSET reloadable=false
CSET rdy=false
# END Parameters
GENERATE