multi_16x16_readme.txt

verilog实现16*16位乘法器

The following files were generated for <multi_16x16> in directory 
D:\My_Designs\example\class7\multiplier\coregen\:

multi_16x16.edn:
   Electronic Data Netlist (EDN) file containing the information
   required to implement the module in a Xilinx (R) FPGA.

multi_16x16.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

multi_16x16.veo:
   VEO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a Verilog design.

multi_16x16.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

multi_16x16_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.

multi_16x16_readme.txt:
   Text file indicating the files generated and how they are used.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.