lin.map.qmsg

verilog HDL 编写的PWM

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 24 00:05:37 2006 " "Info: Processing started: Fri Feb 24 00:05:37 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off lin -c lin " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off lin -c lin" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "lin.v 1 1 " "Info: Using design file lin.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lin " "Info: Found entity 1: lin" {  } { { "F:/PWM/lin.v" "lin" "" { Text "F:/PWM/lin.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "9 8 lin.v(11) " "Warning: Verilog HDL expression warning at lin.v(11): truncated operand with size 9 to match size of smaller operand (8)" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "25 24 lin.v(15) " "Warning: Verilog HDL expression warning at lin.v(15): truncated operand with size 25 to match size of smaller operand (24)" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 9 lin.v(23) " "Warning: Verilog HDL expression warning at lin.v(23): truncated operand with size 10 to match size of smaller operand (9)" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 23 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "base\[4\] data_in GND " "Warning: Reduced register base\[4\] with stuck data_in port to stuck value GND" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "base\[3\] data_in GND " "Warning: Reduced register base\[3\] with stuck data_in port to stuck value GND" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "base\[2\] data_in GND " "Warning: Reduced register base\[2\] with stuck data_in port to stuck value GND" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "base\[1\] data_in GND " "Warning: Reduced register base\[1\] with stuck data_in port to stuck value GND" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "base\[0\] data_in GND " "Warning: Reduced register base\[0\] with stuck data_in port to stuck value GND" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "d:/altera/libraries/megafunctions/lpm_add_sub.tdf" "lpm_add_sub" "" { Text "d:/altera/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "d:/altera/libraries/megafunctions/addcore.tdf" "addcore" "" { Text "d:/altera/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "d:/altera/libraries/megafunctions/a_csnbuffer.tdf" "a_csnbuffer" "" { Text "d:/altera/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "d:/altera/libraries/megafunctions/look_add.tdf" "look_add" "" { Text "d:/altera/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "d:/altera/libraries/megafunctions/altshift.tdf" "altshift" "" { Text "d:/altera/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "32 " "Info: Ignored 32 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "32 " "Info: Ignored 32 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "base\[5\] base\[7\] " "Info: Duplicate register base\[5\] merged to single register base\[7\]" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "base\[6\] base\[7\] " "Info: Duplicate register base\[6\] merged to single register base\[7\]" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "count2\[0\] base\[7\] " "Info: Duplicate register count2\[0\] merged to single register base\[7\]" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock " "Info: Promoted clock signal driven by pin clock to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "60 " "Info: Implemented 60 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "58 " "Info: Implemented 58 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 24 00:05:43 2006 " "Info: Processing ended: Fri Feb 24 00:05:43 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}