lin.tan.summary

来自「verilog HDL 编写的PWM」· SUMMARY 代码 · 共 37 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.000 ns
From           : pwm~reg0
To             : pwm
From Clock     : clock
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : 55.56 MHz ( period = 18.000 ns )
From           : count[1]
To             : count1[11]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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