_info

本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.

m255
cModel Technology
dD:\modelsim 5.8\examples\adder_exam
vadd_ahead
I0:K_B]Y:QZF57@daUi21f2
V<nZN7G6Y4NY7l_JI06R810
dD:\modelsim 5.8\examples\adder_ahead8bit
w1165671772
FD:/modelsim 5.8/examples/adder_ahead8bit/adder_ahead8bit.v
L0 1
OE;L;5.8b;17
r1
31
o-work work