dcache.v

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

         end

        3'h6:
	 begin
          case (DMAS) //synopsys full_case parallel_case
            `DOUB: din_cache = {from_DD,cache_line[191:0]};
            `WORD: din_cache = {cache_line[255:224],from_DD[31:0],cache_line[191:0]};
            `HALF: 
              begin
                case ({BIGEND,byte_sel[1]})  //synopsys full_case parallel_case
                  2'b00, 2'b11:
                    din_cache = {cache_line[255:208],from_DD[15:0],cache_line[191:0]};
                  2'b01, 2'b10:
                    din_cache = {cache_line[255:224],from_DD[31:16],cache_line[207:0]};
                endcase
              end
            `BYTE:
              begin
                case ({BIGEND,byte_sel})  //synopsys full_case parallel_case
                  3'b000,3'b111:
                    din_cache = {cache_line[255:200],from_DD[7:0],cache_line[191:0]};
                  3'b001,3'b110:
                    din_cache = {cache_line[255:208],from_DD[15:8],cache_line[199:0]};
                  3'b010,3'b101:
                    din_cache = {cache_line[255:216],from_DD[23:16],cache_line[207:0]};
                  3'b011,3'b100:
                    din_cache = {cache_line[255:224],from_DD[31:24],cache_line[215:0]};
                endcase
              end
          endcase
         end

	3'h7:
         begin
	  case (DMAS) //synopsys full_case parallel_case
            `DOUB: din_cache = {from_DD[31:0],cache_line[223:0]};
	    `WORD: din_cache = {from_DD[31:0],cache_line[223:0]};
            `HALF:
              begin
                case ({BIGEND,byte_sel[1]})  //synopsys full_case parallel_case
                  2'b00, 2'b11:
                    din_cache = {cache_line[255:240],from_DD[15:0],cache_line[223:0]};
                  2'b01, 2'b10:
                    din_cache = {from_DD[31:16],cache_line[239:0]};
                endcase
              end
            `BYTE: 
              begin
                case ({BIGEND,byte_sel})  //synopsys full_case parallel_case   
                  3'b000,3'b111:
                    din_cache = {cache_line[255:232],from_DD[7:0],cache_line[223:0]}; 
                  3'b001,3'b110:
                    din_cache = {cache_line[255:240],from_DD[15:8],cache_line[231:0]};
                  3'b010,3'b101:
                    din_cache = {cache_line[255:248],from_DD[23:16],cache_line[239:0]};
                  3'b011,3'b100:
                    din_cache = {from_DD[31:24],cache_line[247:0]};
                endcase
              end
          endcase
         end
      endcase
    end	
    else
      din_cache = next_line;
  end
end

//Mux out the Proper Words to the Processor
always @(word_sel or cache_line or lowword or held)
  begin
    case (word_sel) //synopsys full_case parallel_case
      3'b000: to_DD = (held) ? {cache_line[31:0],lowword}
			     : cache_line[63:0];
      3'b001: to_DD = cache_line[95:32]; 
      3'b010: to_DD = cache_line[127:64];
      3'b011: to_DD = cache_line[159:96]; 
      3'b100: to_DD = cache_line[191:128];
      3'b101: to_DD = cache_line[223:160];
      3'b110: to_DD = cache_line[255:192];
      3'b111: to_DD = {32'h0, cache_line[255:224]};
    endcase
  end

//Mux out the Proper Word to Main Memory
always @(word_cntr or cache_line)
  begin
    case (word_cntr) //synopsys full_case parallel_case
      3'b000: to_MMD <= cache_line[31:0];
      3'b001: to_MMD <= cache_line[63:32];
      3'b010: to_MMD <= cache_line[95:64];
      3'b011: to_MMD <= cache_line[127:96];
      3'b100: to_MMD <= cache_line[159:128];
      3'b101: to_MMD <= cache_line[191:160];
      3'b110: to_MMD <= cache_line[223:192];
      3'b111: to_MMD <= cache_line[255:224];
    endcase
  end

//Determine what to put in the line buffer on a miss
always @(word_cntr or cache_line or MMD or mmd_valid or cache_line)
  begin
    if (mmd_valid)
      begin
        case (word_cntr) //synopsys full_case parallel_case
          3'h0: next_line = {cache_line[255:32], MMD};
          3'h1: next_line = {cache_line[255:64], MMD, cache_line[31:0]};
          3'h2: next_line = {cache_line[255:96], MMD, cache_line[63:0]};
          3'h3: next_line = {cache_line[255:128], MMD, cache_line[95:0]};
          3'h4: next_line = {cache_line[255:160], MMD, cache_line[127:0]};
          3'h5: next_line = {cache_line[255:192], MMD, cache_line[159:0]};
          3'h6: next_line = {cache_line[255:224], MMD, cache_line[191:0]};
          3'h7: next_line = {MMD, cache_line[223:0]};
        endcase
      end
    else
       next_line = cache_line;
  end

//Mux the Data into the Tag Cache
always @(tag_line or word_cntr or page_sel or drive_MMD 
		or wb_done or init_on or swic_store or swic_a)
  begin
    if (swic_store)
      din_tag = {2'b01, swic_a[31:`DPSL]};
    else
      begin
        if (init_on | wb_done)
          din_tag = {2'h0, page_sel[`DPSH-1:0]};

        else if (word_cntr == 3'h7 & ~drive_MMD)
          din_tag = {1'b0, page_sel};

        else
          din_tag = {2'h3, tag_line[`DPSH:0]};
      end
  end

//Figure out Which Line to Read
//1) If a double across the boundary, line_sel + 1
//2) During Stalls, read_sel loaded in line_sel
//3) Else DA Bus
always @(doublehold or line_sel or DA or istall or dmiss 
		or swic or swic_store or swic_a
		or flush or flush_wb)
  begin
    if (swic | swic_store | flush | flush_wb)
      read_sel <= (swic_store | flush_wb) ? swic_a[`DLSH:5] : DA[`DLSH:5];
    else if (doublehold & ~istall)
      read_sel <= line_sel + 1;
    else if (istall | dmiss)
      read_sel <= line_sel;
    else
      read_sel <= DA[`DLSH:5];
  end

always @(dwb or decomp or comp_tag_line or
                line_sel or read_sel or flush_wb)
  begin
    if (dwb & decomp)
      line_wb <= comp_tag_line;
    else if (flush_wb)
      line_wb <= read_sel;
    else
      line_wb <= line_sel;
  end

//Which Line Do we Access?
always @(swic_store or swic_a or line_sel or flush_wb)
  begin
    if (swic_store | flush_wb)
      ls_mux <= swic_a[`DLSH:5];
    else
      ls_mux <= line_sel;
  end

/*------------------------------------------------------------------------
        Sequential Always Block
------------------------------------------------------------------------*/
//synopsys async_set_reset nRESET
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      init_on <= 1'b1;
    else if (init_done)
      init_on <= 1'b0;
  end

//Reading Cache?
//synopsys async_set_reset nRESET
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      access <= #1 1'b0;
    else if (nMiss_active & ~istall & ~doublehold)
      access <= #1 ~DnMREQ & ~DABORT;
  end

//Writing Cache?
//synopsys async_set_reset nRESET
always @(posedge nGCLK or negedge nRESET)
  begin
   if (~nRESET)
     writecycle <= #1 1'b0;
   else if (nMiss_active & ~istall & ~doublehold)
     writecycle <= #1 ~DnMREQ & ~DnWR;
  end

//Latch the Busses for SWIC Instructions
//synopsys async_set_reset nRESET
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      begin
        swic_d <= 32'h0;
        swic_a <= 30'h0;
      end
    else if (swic | (flush & ~dmiss))
      begin
        swic_d <= swic_data;
        swic_a <= DA[31:2];
      end
  end

//Latch the SWIC signal
//synopsys async_set_reset nRESET
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      swic_store <= 1'b0;
    else if (~dmiss & ~doublehold)
      swic_store <= swic;
  end

//Latch the FLUSH signal
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      flush_now <= 1'b0;
    else if (~dmiss & ~doublehold)
      flush_now <= flush;
  end

//Watch out for DoubleLine Access
//synopsys async_set_reset nRESET
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      held <= #1 1'b0;
    else if (~istall)
      held <= #1 doublehold | (held & ~nMiss_active);
  end

//Data Bus Driver
//synopsys async_set_reset nRESET
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      drive_DD <= #1 1'b0;
    else if (nMiss_active & ~istall & ~doublehold)
      drive_DD <= #1 ~DnMREQ & DnWR;
  end

//Memory Bus Driver
//synopsys async_set_reset nRESET
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      drive_MMD <= #1 1'b0;
    else
      drive_MMD <= #1 drive_mmd;
  end

//Latch the Address Bits to Appropriate Regs
always @(posedge nGCLK)
  begin
    if (~DnMREQ & nMiss_active & ~istall)
      begin
	  byte_sel <= #1 DA[1:0];
      end
  end

//Latch the Address Bits to Appropriate Regs
//synopsys async_set_reset nRESET
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      begin
        line_sel <= 9'h0;
        word_sel <= 3'h0;
        page_sel <= 0;
      end
 
    else if (((~DnMREQ | doublehold) & nMiss_active & ~istall) | init_on)
      begin
        line_sel <= #1 (doublehold | init_on) ? (line_sel + 1)  
                                              : DA[`DLSH:5];
        word_sel <= #1 (doublehold) ? (word_sel + 1)
                                    : DA[4:2];
        page_sel <= #1 (doublehold) ? (page_sel + ls_and)
			            : {1'b1, DA[31:`DPSL]};
      end
  end

//Disable latch for DD bus
always @(istall or doublehold or nGCLK)
  begin
    if (~nGCLK)
      disable_latch <= istall | doublehold;
  end

//Latch the Data Bus
always @(nGCLK or DD or disable_latch or nMiss_active or from_DD)
  begin
    if (nGCLK)
      begin
        if (~disable_latch & nMiss_active)
          from_DD <= DD;
        else
          from_DD <= from_DD;
      end
  end

//Stall the Processor on a cache miss
//synopsys async_set_reset "nRESET"
always @(nGCLK or dmiss or nRESET)
  begin
    if (~nRESET)
      nMiss_active <= 1'b1;
    else if (~nGCLK)
      nMiss_active <= ~(dmiss & ~DABORT);
  end

//Cache Miss Word Count
//synopsys async_set_reset nRESET
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      word_cntr <= 3'h0;
    else if (~nMiss_active & ((mmd_valid & ~dwb) | (drive_MMD & dwb)))
      word_cntr <= word_cntr + 1;
    else
      word_cntr <= 3'h0;
  end

//synopsys async_set_reset nRESET
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      wb_done <= 1'b0;
    else
      wb_done <= ((word_cntr == 3'h6) & dwb);
  end

//Grab the low order word on a Double
//Word Access across Line Boundaries
//synopsys async_set_reset nRESET
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      lowword <= 32'h0000000;
    else if (doublehold)
      lowword <= (writecycle) ? from_DD[63:32] 
			      : next_line[255:224];
  end

//Create a Single Line Register for use in Data Decompression
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      comp_line <= {256{1'b0}};
    else if (wr_ena_cc)
      comp_line <= din_cache;
  end

//Create a Single Line Tag for use in Data Decompression
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      begin
        comp_tag <= {`DTS{1'b0}};
        comp_tag_line <= line_sel;
      end
    else if (wr_ena_ct)
      begin
        comp_tag <= din_tag;
        comp_tag_line <= line_sel;
      end
  end


endmodule