lec25dscc25.v

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

	or _wi3 (_wn3,_wn4,DIN4);
	and _wi4 (_wn1,_wn2,_wn3);
	not _wi5 (_wn9,DIN5);
	and _wi6 (_wn8,DIN4,_wn9);
	or _wi8 (_wn7,_wn8,_wn5);
	and _wi9 (_wn6,DIN3,_wn7);
	or _wi10 (DIN2Qstate0,_wn1,_wn6);
	specify	(DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	(DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	(DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	(DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(!DIN3&!DIN4&!DIN5) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate0) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	endspecify
endmodule
`endcelldefine
// Copyright 1998-1999 LEDA Systems, Inc.
`celldefine
// 2/3 and-or-invert gate, 2x
// Q = !((DIN1 & DIN2) | (DIN3 & DIN4 & DIN5))
module aoi23s2 (Q, DIN1, DIN2, DIN3, DIN4, DIN5);
	output Q;
	input  DIN1;
	input  DIN2;
	input  DIN3;
	input  DIN4;
	input  DIN5;
	and _i0 (_n1,DIN1,DIN2);
	and _i1 (_n2,DIN5,DIN3,DIN4);
	nor _i2 (Q,_n1,_n2);
	not _wi0 (_wn2,DIN3);
	not _wi1 (_wn5,DIN4);
	and _wi2 (_wn4,_wn5,DIN5);
	or _wi3 (_wn3,_wn4,DIN4);
	and _wi4 (_wn1,_wn2,_wn3);
	not _wi5 (_wn9,DIN5);
	and _wi6 (_wn8,DIN4,_wn9);
	or _wi8 (_wn7,_wn8,_wn5);
	and _wi9 (_wn6,DIN3,_wn7);
	or _wi10 (DIN1Qstate0,_wn1,_wn6);
	or _wi21 (DIN2Qstate0,_wn1,_wn6);
	specify	(DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	(DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	(DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(!DIN3&!DIN4&!DIN5) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(!DIN3&!DIN4&!DIN5) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN1Qstate0) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate0) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	endspecify
endmodule
`endcelldefine
// Copyright 1998-1999 LEDA Systems, Inc.
`celldefine
// 2/3 and-or-invert gate, 3x
// Q = !((DIN1 & DIN2) | (DIN3 & DIN4 & DIN5))
module aoi23s3 (Q, DIN1, DIN2, DIN3, DIN4, DIN5);
	output Q;
	input  DIN1;
	input  DIN2;
	input  DIN3;
	input  DIN4;
	input  DIN5;
	and _i0 (_n1,DIN1,DIN2);
	and _i1 (_n2,DIN5,DIN3,DIN4);
	nor _i2 (Q,_n1,_n2);
	not _wi0 (_wn2,DIN3);
	and _wi1 (_wn1,DIN5,_wn2,DIN4);
	not _wi2 (_wn6,DIN4);
	and _wi3 (_wn5,_wn6,DIN5);
	not _wi4 (_wn8,DIN5);
	and _wi5 (_wn7,DIN4,_wn8);
	or _wi6 (_wn4,_wn5,_wn7);
	and _wi7 (_wn3,DIN3,_wn4);
	or _wi8 (DIN1Qstate0,_wn1,_wn3);
	or _wi13 (_wn12,_wn7,_wn6);
	and _wi14 (_wn10,_wn2,_wn12);
	and _wi17 (_wn16,_wn8,DIN3,_wn6);
	or _wi18 (DIN2Qstate1,_wn10,_wn16);
	not _wi19 (_wn21,DIN1);
	and _wi20 (_wn20,_wn21,DIN2);
	not _wi21 (_wn23,DIN2);
	and _wi22 (_wn22,DIN1,_wn23);
	or _wi23 (DIN5Qstate0,_wn20,_wn22);
	or _wi28 (DIN4Qstate0,_wn20,_wn22);
	or _wi38 (DIN1Qstate1,_wn10,_wn16);
	or _wi43 (DIN3Qstate0,_wn20,_wn22);
	or _wi52 (DIN2Qstate0,_wn1,_wn3);
	specify	if(!DIN1&!DIN2) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(!DIN1&!DIN2) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(!DIN1&!DIN2) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN1Qstate0) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN1Qstate1) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate0) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate1) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate0) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate0) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate0) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	endspecify
endmodule
`endcelldefine
// Copyright 1998-1999 LEDA Systems, Inc.
`celldefine
// 3/3 AND-OR-Invert Gate, 1x
// Q = !((DIN1 & DIN2 & DIN3) | (DIN4 & DIN5 & DIN6))
module aoi33s1 (Q, DIN1, DIN2, DIN3, DIN4, DIN5, DIN6);
	output Q;
	input  DIN1;
	input  DIN2;
	input  DIN3;
	input  DIN4;
	input  DIN5;
	input  DIN6;
	and _i0 (_n1,DIN3,DIN1,DIN2);
	and _i1 (_n2,DIN6,DIN4,DIN5);
	nor _i2 (Q,_n1,_n2);
	not _wi0 (_wn2,DIN4);
	and _wi1 (_wn1,_wn2,DIN6);
	not _wi2 (_wn6,DIN5);
	and _wi3 (_wn5,_wn6,DIN6);
	not _wi4 (_wn8,DIN6);
	and _wi5 (_wn7,DIN5,_wn8);
	or _wi6 (_wn4,_wn5,_wn7);
	and _wi7 (_wn3,DIN4,_wn4);
	or _wi8 (DIN1Qstate0,_wn1,_wn3);
	not _wi9 (_wn11,DIN1);
	not _wi10 (_wn12,DIN3);
	and _wi11 (_wn10,_wn11,_wn12);
	not _wi13 (_wn15,DIN2);
	and _wi14 (_wn13,_wn12,DIN1,_wn15);
	or _wi15 (DIN4Qstate1,_wn10,_wn13);
	and _wi18 (_wn17,_wn2,_wn8);
	and _wi21 (_wn20,_wn8,DIN4,_wn6);
	or _wi22 (DIN3Qstate1,_wn17,_wn20);
	or _wi29 (DIN2Qstate1,_wn17,_wn20);
	or _wi36 (DIN1Qstate1,_wn17,_wn20);
	and _wi39 (_wn41,_wn15,DIN3);
	or _wi40 (_wn40,_wn41,DIN2);
	and _wi41 (_wn38,_wn11,_wn40);
	and _wi43 (_wn45,DIN2,_wn12);
	or _wi45 (_wn44,_wn45,_wn15);
	and _wi46 (_wn43,DIN1,_wn44);
	or _wi47 (DIN6Qstate0,_wn38,_wn43);
	or _wi58 (DIN5Qstate0,_wn38,_wn43);
	and _wi60 (_wn60,_wn11,DIN3);
	or _wi65 (_wn63,_wn41,_wn45);
	and _wi66 (_wn62,DIN1,_wn63);
	or _wi67 (DIN4Qstate0,_wn60,_wn62);
	or _wi76 (DIN3Qstate0,_wn1,_wn3);
	or _wi85 (DIN2Qstate0,_wn1,_wn3);
	specify	if(!DIN1&!DIN2&!DIN3) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(!DIN1&!DIN2&!DIN3) (DIN6 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN1Qstate0) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN1Qstate1) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate0) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate1) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate0) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate1) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate0) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate1) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate0) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN6Qstate0) (DIN6 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	endspecify
endmodule
`endcelldefine
// Copyright 1998-1999 LEDA Systems, Inc.
`celldefine
// 3/3 AND-OR-Invert Gate, 2x
// Q = !((DIN1 & DIN2 & DIN3) | (DIN4 & DIN5 & DIN6))
module aoi33s2 (Q, DIN1, DIN2, DIN3, DIN4, DIN5, DIN6);
	output Q;
	input  DIN1;
	input  DIN2;
	input  DIN3;
	input  DIN4;
	input  DIN5;
	input  DIN6;
	and _i0 (_n1,DIN3,DIN1,DIN2);
	and _i1 (_n2,DIN6,DIN4,DIN5);
	nor _i2 (Q,_n1,_n2);
	not _wi0 (_wn2,DIN4);
	and _wi1 (_wn1,DIN6,_wn2,DIN5);
	not _wi2 (_wn6,DIN5);
	and _wi3 (_wn5,_wn6,DIN6);
	not _wi4 (_wn8,DIN6);
	and _wi5 (_wn7,DIN5,_wn8);
	or _wi6 (_wn4,_wn5,_wn7);
	and _wi7 (_wn3,DIN4,_wn4);
	or _wi8 (DIN1Qstate0,_wn1,_wn3);
	not _wi9 (_wn11,DIN1);
	not _wi10 (_wn12,DIN3);
	and _wi11 (_wn10,_wn11,_wn12);
	not _wi13 (_wn15,DIN2);
	and _wi14 (_wn13,_wn12,DIN1,_wn15);
	or _wi15 (DIN6Qstate1,_wn10,_wn13);
	and _wi18 (_wn20,DIN2,_wn12);
	or _wi20 (_wn19,_wn20,_wn15);
	and _wi21 (_wn17,_wn11,_wn19);
	or _wi25 (DIN5Qstate1,_wn17,_wn13);
	or _wi35 (DIN4Qstate1,_wn17,_wn13);
	and _wi38 (_wn37,_wn2,_wn8);
	and _wi41 (_wn40,_wn8,DIN4,_wn6);
	or _wi42 (DIN3Qstate1,_wn37,_wn40);
	or _wi47 (_wn46,_wn7,_wn6);
	and _wi48 (_wn44,_wn2,_wn46);
	or _wi52 (DIN2Qstate1,_wn44,_wn40);
	or _wi62 (DIN1Qstate1,_wn44,_wn40);
	and _wi64 (_wn64,_wn11,DIN3);
	and _wi66 (_wn68,_wn15,DIN3);
	or _wi69 (_wn67,_wn68,_wn20);
	and _wi70 (_wn66,DIN1,_wn67);
	or _wi71 (DIN6Qstate0,_wn64,_wn66);
	and _wi73 (_wn73,DIN3,_wn11,DIN2);
	or _wi80 (DIN5Qstate0,_wn73,_wn66);
	or _wi89 (DIN4Qstate0,_wn73,_wn66);
	and _wi91 (_wn91,_wn2,DIN6);
	or _wi98 (DIN3Qstate0,_wn91,_wn3);
	or _wi107 (DIN2Qstate0,_wn1,_wn3);
	specify	if(DIN1Qstate0) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN1Qstate1) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate0) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate1) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate0) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate1) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate0) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate1) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate0) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate1) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN6Qstate0) (DIN6 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN6Qstate1) (DIN6 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	endspecify
endmodule
`endcelldefine
// Copyright 1998-1999 LEDA Systems, Inc.
`celldefine
// 3/3 AND-OR-Invert Gate, 3x
// Q = !((DIN1 & DIN2 & DIN3) | (DIN4 & DIN5 & DIN6))
module aoi33s3 (Q, DIN1, DIN2, DIN3, DIN4, DIN5, DIN6);
	output Q;
	input  DIN1;
	input  DIN2;
	input  DIN3;
	input  DIN4;
	input  DIN5;
	input  DIN6;
	and _i0 (_n1,DIN3,DIN1,DIN2);
	and _i1 (_n2,DIN6,DIN4,DIN5);
	nor _i2 (Q,_n1,_n2);
	not _wi0 (_wn2,DIN4);
	and _wi1 (_wn1,DIN6,_wn2,DIN5);
	not _wi2 (_wn6,DIN5);
	and _wi3 (_wn5,_wn6,DIN6);
	not _wi4 (_wn8,DIN6);
	and _wi5 (_wn7,DIN5,_wn8);
	or _wi6 (_wn4,_wn5,_wn7);
	and _wi7 (_wn3,DIN4,_wn4);
	or _wi8 (DIN1Qstate0,_wn1,_wn3);
	not _wi9 (_wn11,DIN1);
	not _wi10 (_wn14,DIN3);
	and _wi11 (_wn13,DIN2,_wn14);
	not _wi12 (_wn15,DIN2);
	or _wi13 (_wn12,_wn13,_wn15);
	and _wi14 (_wn10,_wn11,_wn12);
	and _wi17 (_wn16,_wn14,DIN1,_wn15);
	or _wi18 (DIN6Qstate1,_wn10,_wn16);
	or _wi28 (DIN5Qstate1,_wn10,_wn16);
	or _wi38 (DIN4Qstate1,_wn10,_wn16);
	or _wi43 (_wn42,_wn7,_wn6);
	and _wi44 (_wn40,_wn2,_wn42);
	and _wi47 (_wn46,_wn8,DIN4,_wn6);
	or _wi48 (DIN3Qstate1,_wn40,_wn46);
	or _wi58 (DIN2Qstate1,_wn40,_wn46);
	or _wi68 (DIN1Qstate1,_wn40,_wn46);
	and _wi70 (_wn70,DIN3,_wn11,DIN2);
	and _wi72 (_wn74,_wn15,DIN3);
	or _wi75 (_wn73,_wn74,_wn13);
	and _wi76 (_wn72,DIN1,_wn73);
	or _wi77 (DIN6Qstate0,_wn70,_wn72);
	or _wi86 (DIN5Qstate0,_wn70,_wn72);
	or _wi95 (DIN4Qstate0,_wn70,_wn72);
	or _wi104 (DIN3Qstate0,_wn1,_wn3);
	or _wi113 (DIN2Qstate0,_wn1,_wn3);
	specify	if(DIN1Qstate0) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN1Qstate1) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate0) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate1) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate0) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate1) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate0) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate1) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate0) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate1) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN6Qstate0) (DIN6 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN6Qstate1) (DIN6 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	endspecify
endmodule
`endcelldefine
// Copyright 1998-1999 LEDA Systems, Inc.
`celldefine
// 4/1/1/1 AND-OR-Invert Gate, 1x
// Q = !((DIN1 & DIN2 & DIN3 & DIN4) | DIN5 | DIN6 | DIN7)
module aoi4111s1 (Q, DIN1, DIN2, DIN3, DIN4, DIN5, DIN6, DIN7);
	output Q;
	input  DIN1;
	input  DIN2;
	input  DIN3;
	input  DIN4;
	input  DIN5;
	input  DIN6;
	input  DIN7;
	and _i0 (_n1,DIN4,DIN3,DIN1,DIN2);
	nor _i1 (Q,DIN7,DIN6,_n1,DIN5);
	not _wi0 (_wn2,DIN1);
	not _wi1 (_wn5,DIN2);
	and _wi2 (_wn4,_wn5,DIN4);
	not _wi3 (_