lec25dscc25.v

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

	input  DIN1;
	input  DIN2;
	input  DIN3;
	input  DIN4;
	input  DIN5;
	and _i0 (_n1,DIN1,DIN2);
	and _i1 (_n2,DIN3,DIN4);
	nor _i2 (Q,DIN5,_n1,_n2);
	not _wi0 (_wn1,DIN4);
	not _wi1 (_wn2,DIN3);
	not _wi2 (_wn3,DIN1);
	not _wi3 (_wn4,DIN2);
	and _wi4 (DIN5Qstate1,_wn1,_wn2,_wn3,_wn4);
	and _wi8 (_wn12,_wn2,DIN4);
	and _wi10 (_wn14,DIN3,_wn1);
	or _wi11 (_wn11,_wn12,_wn14);
	and _wi12 (_wn9,_wn4,_wn11);
	or _wi16 (_wn17,_wn14,_wn2);
	and _wi17 (_wn16,DIN2,_wn17);
	or _wi18 (_wn8,_wn9,_wn16);
	and _wi19 (_wn6,_wn3,_wn8);
	and _wi25 (_wn21,DIN1,_wn4,_wn17);
	or _wi26 (DIN5Qstate0,_wn6,_wn21);
	specify	(DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	(DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	(DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	(DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate0) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate1) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	endspecify
endmodule
`endcelldefine
// Copyright 1998-1999 LEDA Systems, Inc.
`celldefine
// 2/2/1 and-or-invert gate, 3x
// Q = !((DIN1 & DIN2) | (DIN3 & DIN4) | DIN5)
module aoi221s3 (Q, DIN1, DIN2, DIN3, DIN4, DIN5);
	output Q;
	input  DIN1;
	input  DIN2;
	input  DIN3;
	input  DIN4;
	input  DIN5;
	and _i0 (_n1,DIN1,DIN2);
	and _i1 (_n2,DIN3,DIN4);
	nor _i2 (Q,DIN5,_n1,_n2);
	specify	(DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	(DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	(DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	(DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	(DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	endspecify
endmodule
`endcelldefine
// Copyright 1998-1999 LEDA Systems, Inc.
`celldefine
// 2/2/2/1 AND-OR-Invert Gate, 1x
// Q = !((DIN1 & DIN2) | (DIN3 & DIN4) | (DIN5 & DIN6) | DIN7)
module aoi2221s1 (Q, DIN1, DIN2, DIN3, DIN4, DIN5, DIN6, DIN7);
	output Q;
	input  DIN1;
	input  DIN2;
	input  DIN3;
	input  DIN4;
	input  DIN5;
	input  DIN6;
	input  DIN7;
	and _i0 (_n1,DIN1,DIN2);
	and _i1 (_n2,DIN3,DIN4);
	and _i2 (_n3,DIN5,DIN6);
	nor _i3 (Q,DIN7,_n1,_n2,_n3);
	not _wi0 (_wn2,DIN3);
	not _wi1 (_wn5,DIN5);
	and _wi2 (_wn4,_wn5,DIN6);
	not _wi3 (_wn7,DIN6);
	and _wi4 (_wn6,DIN5,_wn7);
	or _wi5 (_wn3,_wn4,_wn6);
	and _wi6 (_wn1,_wn2,DIN4,_wn3);
	not _wi7 (_wn9,DIN4);
	and _wi13 (_wn8,DIN3,_wn9,_wn3);
	or _wi14 (DIN1Qstate0,_wn1,_wn8);
	not _wi15 (_wn17,DIN1);
	not _wi16 (_wn20,DIN2);
	and _wi18 (_wn19,_wn20,_wn2);
	and _wi21 (_wn22,_wn9,DIN2,_wn2);
	or _wi22 (_wn18,_wn19,_wn22);
	and _wi23 (_wn16,_wn17,_wn18);
	and _wi27 (_wn25,_wn9,_wn2,DIN1,_wn20);
	or _wi28 (DIN6Qstate1,_wn16,_wn25);
	and _wi36 (_wn33,_wn20,_wn3);
	and _wi39 (_wn40,_wn7,DIN2,_wn5);
	or _wi40 (_wn32,_wn33,_wn40);
	and _wi41 (_wn30,_wn17,_wn32);
	and _wi45 (_wn43,_wn7,_wn5,DIN1,_wn20);
	or _wi46 (DIN4Qstate1,_wn30,_wn43);
	and _wi54 (_wn51,_wn9,_wn3);
	and _wi57 (_wn58,_wn7,DIN4,_wn5);
	or _wi58 (_wn50,_wn51,_wn58);
	and _wi59 (_wn48,_wn2,_wn50);
	and _wi63 (_wn61,_wn7,_wn5,DIN3,_wn9);
	or _wi64 (DIN2Qstate1,_wn48,_wn61);
	and _wi70 (DIN7Qstate2,_wn7,_wn5,_wn9,_wn17,_wn2);
	and _wi75 (DIN3Qstate2,_wn7,_wn5,_wn17,_wn20);
	and _wi80 (DIN1Qstate2,_wn7,_wn5,_wn2,_wn9);
	and _wi84 (_wn85,_wn9,_wn20,DIN3);
	and _wi86 (_wn90,_wn2,DIN4);
	and _wi88 (_wn92,DIN3,_wn9);
	or _wi89 (_wn89,_wn90,_wn92);
	and _wi90 (_wn88,DIN2,_wn89);
	or _wi91 (_wn84,_wn85,_wn88);
	and _wi92 (_wn82,_wn17,_wn84);
	and _wi99 (_wn94,DIN1,_wn20,_wn89);
	or _wi100 (DIN6Qstate0,_wn82,_wn94);
	and _wi107 (_wn102,_wn17,DIN2,_wn3);
	and _wi114 (_wn109,DIN1,_wn20,_wn3);
	or _wi115 (DIN4Qstate0,_wn102,_wn109);
	or _wi130 (DIN2Qstate0,_wn1,_wn8);
	and _wi142 (_wn148,DIN4,_wn5);
	or _wi143 (_wn140,_wn51,_wn148);
	and _wi144 (_wn138,_wn2,_wn140);
	or _wi149 (_wn137,_wn138,_wn61);
	and _wi150 (_wn135,_wn20,_wn137);
	and _wi169 (_wn154,DIN2,DIN2Qstate1);
	or _wi170 (_wn134,_wn135,_wn154);
	and _wi171 (_wn132,_wn17,_wn134);
	and _wi176 (_wn179,_wn9,_wn5);
	or _wi180 (_wn178,_wn179,_wn58);
	and _wi181 (_wn176,_wn2,_wn178);
	or _wi186 (_wn175,_wn176,_wn61);
	and _wi187 (_wn173,DIN1,_wn20,_wn175);
	or _wi188 (DIN7Qstate1,_wn132,_wn173);
	or _wi202 (DIN5Qstate1,_wn16,_wn25);
	or _wi220 (DIN3Qstate1,_wn30,_wn43);
	or _wi238 (DIN1Qstate1,_wn48,_wn61);
	and _wi243 (DIN4Qstate2,_wn7,_wn5,_wn17,_wn20);
	and _wi248 (DIN2Qstate2,_wn7,_wn5,_wn2,_wn9);
	and _wi253 (_wn256,_wn7,DIN5,_wn2,DIN4);
	or _wi261 (_wn255,_wn256,_wn8);
	and _wi262 (_wn253,_wn20,_wn255);
	and _wi278 (_wn266,DIN2,DIN2Qstate0);
	or _wi279 (_wn252,_wn253,_wn266);
	and _wi280 (_wn250,_wn17,_wn252);
	and _wi285 (_wn288,_wn7,_wn9,DIN5);
	and _wi291 (_wn291,DIN4,_wn3);
	or _wi292 (_wn287,_wn288,_wn291);
	and _wi293 (_wn285,_wn2,_wn287);
	or _wi301 (_wn284,_wn285,_wn8);
	and _wi302 (_wn282,DIN1,_wn20,_wn284);
	or _wi303 (DIN7Qstate0,_wn250,_wn282);
	or _wi323 (DIN5Qstate0,_wn82,_wn94);
	or _wi338 (DIN3Qstate0,_wn102,_wn109);
	specify	if(DIN1Qstate0) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN1Qstate1) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN1Qstate2) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate0) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate1) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate2) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate0) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate1) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate2) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate0) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate1) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate2) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate0) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate1) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN6Qstate0) (DIN6 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN6Qstate1) (DIN6 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN7Qstate0) (DIN7 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN7Qstate1) (DIN7 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN7Qstate2) (DIN7 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	endspecify
endmodule
`endcelldefine
// Copyright 1998-1999 LEDA Systems, Inc.
`celldefine
// 2/2/2/1 AND-OR-Invert Gate, 2x
// Q = !((DIN1 & DIN2) | (DIN3 & DIN4) | (DIN5 & DIN6) | DIN7)
module aoi2221s2 (Q, DIN1, DIN2, DIN3, DIN4, DIN5, DIN6, DIN7);
	output Q;
	input  DIN1;
	input  DIN2;
	input  DIN3;
	input  DIN4;
	input  DIN5;
	input  DIN6;
	input  DIN7;
	and _i0 (_n1,DIN1,DIN2);
	and _i1 (_n2,DIN3,DIN4);
	and _i2 (_n3,DIN5,DIN6);
	nor _i3 (Q,DIN7,_n1,_n2,_n3);
	not _wi0 (_wn2,DIN3);
	not _wi1 (_wn5,DIN5);
	and _wi2 (_wn4,_wn5,DIN6);
	not _wi3 (_wn7,DIN6);
	and _wi4 (_wn6,DIN5,_wn7);
	or _wi5 (_wn3,_wn4,_wn6);
	and _wi6 (_wn1,_wn2,DIN4,_wn3);
	not _wi7 (_wn9,DIN4);
	and _wi13 (_wn8,DIN3,_wn9,_wn3);
	or _wi14 (DIN1Qstate0,_wn1,_wn8);
	not _wi15 (_wn17,DIN1);
	not _wi16 (_wn20,DIN2);
	and _wi18 (_wn22,_wn2,DIN4);
	and _wi20 (_wn24,DIN3,_wn9);
	or _wi21 (_wn21,_wn22,_wn24);
	and _wi22 (_wn19,_wn20,_wn21);
	and _wi25 (_wn26,_wn9,DIN2,_wn2);
	or _wi26 (_wn18,_wn19,_wn26);
	and _wi27 (_wn16,_wn17,_wn18);
	and _wi31 (_wn29,_wn9,_wn2,DIN1,_wn20);
	or _wi32 (DIN6Qstate1,_wn16,_wn29);
	and _wi40 (_wn37,_wn20,_wn3);
	and _wi43 (_wn44,_wn7,DIN2,_wn5);
	or _wi44 (_wn36,_wn37,_wn44);
	and _wi45 (_wn34,_wn17,_wn36);
	and _wi49 (_wn47,_wn7,_wn5,DIN1,_wn20);
	or _wi50 (DIN4Qstate1,_wn34,_wn47);
	and _wi58 (_wn55,_wn9,_wn3);
	and _wi61 (_wn62,_wn7,DIN4,_wn5);
	or _wi62 (_wn54,_wn55,_wn62);
	and _wi63 (_wn52,_wn2,_wn54);
	and _wi67 (_wn65,_wn7,_wn5,DIN3,_wn9);
	or _wi68 (DIN2Qstate1,_wn52,_wn65);
	and _wi89 (_wn73,_wn20,DIN2Qstate1);
	and _wi94 (_wn93,_wn7,_wn5,_wn9,DIN2,_wn2);
	or _wi95 (_wn72,_wn73,_wn93);
	and _wi96 (_wn70,_wn17,_wn72);
	and _wi102 (_wn98,_wn7,_wn5,_wn9,_wn2,DIN1,_wn20);
	or _wi103 (DIN7Qstate2,_wn70,_wn98);
	and _wi108 (DIN5Qstate2,_wn9,_wn2,_wn17,_wn20);
	and _wi113 (DIN3Qstate2,_wn7,_wn5,_wn17,_wn20);
	and _wi118 (DIN1Qstate2,_wn7,_wn5,_wn2,_wn9);
	and _wi125 (_wn120,_wn17,DIN2,_wn21);
	and _wi132 (_wn127,DIN1,_wn20,_wn21);
	or _wi133 (DIN6Qstate0,_wn120,_wn127);
	and _wi140 (_wn135,_wn17,DIN2,_wn3);
	and _wi147 (_wn142,DIN1,_wn20,_wn3);
	or _wi148 (DIN4Qstate0,_wn135,_wn142);
	or _wi163 (DIN2Qstate0,_wn1,_wn8);
	and _wi181 (_wn168,_wn20,DIN2Qstate0);
	and _wi200 (_wn185,DIN2,DIN2Qstate1);
	or _wi201 (_wn167,_wn168,_wn185);
	and _wi202 (_wn165,_wn17,_wn167);
	and _wi222 (_wn204,DIN1,_wn20,DIN2Qstate1);
	or _wi223 (DIN7Qstate1,_wn165,_wn204);
	or _wi241 (DIN5Qstate1,_wn16,_wn29);
	or _wi259 (DIN3Qstate1,_wn34,_wn47);
	and _wi264 (DIN6Qstate2,_wn9,_wn2,_wn17,_wn20);
	or _wi282 (DIN1Qstate1,_wn52,_wn65);
	and _wi287 (DIN4Qstate2,_wn7,_wn5,_wn17,_wn20);
	and _wi294 (DIN7Qstate3,_wn7,_wn5,_wn9,_wn2,_wn17,_wn20);
	and _wi299 (DIN2Qstate2,_wn7,_wn5,_wn2,_wn9);
	and _wi316 (_wn301,_wn17,DIN2,DIN2Qstate0);
	and _wi333 (_wn318,DIN1,_wn20,DIN2Qstate0);
	or _wi334 (DIN7Qstate0,_wn301,_wn318);
	or _wi349 (DIN5Qstate0,_wn120,_wn127);
	or _wi364 (DIN3Qstate0,_wn135,_wn142);
	specify	if(DIN1Qstate0) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN1Qstate1) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN1Qstate2) (DIN1 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate0) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate1) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN2Qstate2) (DIN2 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate0) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate1) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN3Qstate2) (DIN3 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate0) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate1) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN4Qstate2) (DIN4 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate0) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate1) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN5Qstate2) (DIN5 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN6Qstate0) (DIN6 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN6Qstate1) (DIN6 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN6Qstate2) (DIN6 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN7Qstate0) (DIN7 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN7Qstate1) (DIN7 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN7Qstate2) (DIN7 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	if(DIN7Qstate3) (DIN7 => Q) = (`ifdef unit_delay 1 `else 0 `endif ,`ifdef unit_delay 1 `else 0 `endif );
	endspecify
endmodule
`endcelldefine
// Copyright 1998-1999 LEDA Systems, Inc.
`celldefine
// 2/2/2/1 AND-OR-Invert Gate, 3x
// Q = !((DIN1 & DIN2) | (DIN3 & DIN4) | (DIN5 & DIN6) | DIN7)
module aoi2221s3 (Q, DIN1, DIN2, DIN3, DIN4, DIN5, DIN6, DIN7);
	output Q;
	input  DIN1;
	input  DIN2;
	input  DIN3;
	input  DIN4;
	input  DIN5;
	input  DIN6;
	input  DIN7;
	and _i0 (_n1,DIN1,DIN2);
	and _i1 (_n2,DIN3,DIN4);
	and _i2 (_n3,DIN5,DIN6);
	nor _i3 (Q,DIN7,_n1,_n2,_n3);
	not _wi0 (_wn2,DIN3);
	not _wi1 (_wn5,DIN5);
	and _wi2 (_wn4,_wn5,DIN6);
	not _wi3 (_wn7,DIN6);
	and _wi4 (_wn6,DIN5,_wn7);
	or _wi5 (_wn3,_wn4,_wn6);
	and _wi6 (_wn1,_wn2,DIN4,_wn3);
	not _wi7 (_wn9,DIN4);
	and _wi13 (_wn8,DIN3,_wn9,_wn3);
	or _wi14 (DIN1Qstate0,_wn1,_wn8);
	not _wi15 (_wn17,DIN1);
	not _wi16 (_wn20,DIN2);
	and _wi18 (_wn22,_wn2,DIN4);
	and _wi20 (_wn24,DIN3,_wn9);
	or _wi21 (_wn21,_wn22,_wn24);
	and _wi22 (_wn19,_wn20,_wn21);
	and _wi25 (_wn26,_wn9,DIN2,_wn2);
	or _wi26 (_wn18,_wn19,_wn26);