phase_test.v

verilog编写基于fpga的鉴相器模块

module phase_test(
			clk,
			combphasein,
			cs,
			phase_sig,			
			gatein,
			clkcountin,
			COUNTNUM,
			sclr,
			PLLEN
			);
input clk;
input combphasein;
input cs;
input [1:0] phase_sig;
input [15:0] gatein;
input [31:0] clkcountin;
output reg [31:0] COUNTNUM;
output reg sclr;
output reg PLLEN;

reg [15:0] gatelim;
reg countstart,countstop;
reg [15:0] counttemp;


reg [1:0] state;
parameter 	IDLE 	=2'b01,
			COUNT	=2'b10;

always @(posedge clk)
begin
if (cs)
	begin
	state<=IDLE;
	gatelim<=0;
	countstart<=0;
	PLLEN<=0;
	end
else	
case(state)
default:	begin					
		sclr<=1;
		countstart<=0;			
		case (phase_sig)
		2'b01:	begin
				gatelim<=gatein;
				countstart<=1;
				state<=COUNT;
				end
		2'b10:	begin
				PLLEN<=1;
				end		
		default:	state<=IDLE;
		endcase
		end
COUNT:	begin
		sclr<=0;
		if (countstop)
			begin
			countstart<=0;
			COUNTNUM<=clkcountin;
			PLLEN<=0;
			state<=IDLE;
			end
		else
			state<=COUNT;
		end
endcase	
end			
		
always @(negedge combphasein)
begin
if (countstart)
	begin
	if (counttemp==gatelim)
		begin
		countstop<=1;
		end
	else
		begin	
		countstop<=0;
		counttemp<=counttemp+1;
		end
	end	
else 	
	begin
	countstop<=0;
	counttemp<=1;
	end
end

endmodule