phase_test.tan.qmsg

verilog编写基于fpga的鉴相器模块

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "phaseinA register phase_test:inst\|counttemp\[15\] register phase_test:inst\|counttemp\[15\] 127.8 MHz 7.825 ns Internal " "Info: Clock \"phaseinA\" has Internal fmax of 127.8 MHz between source register \"phase_test:inst\|counttemp\[15\]\" and destination register \"phase_test:inst\|counttemp\[15\]\" (period= 7.825 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.564 ns + Longest register register " "Info: + Longest register to register delay is 7.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns phase_test:inst\|counttemp\[15\] 1 REG LC_X27_Y8_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y8_N7; Fanout = 2; REG Node = 'phase_test:inst\|counttemp\[15\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_test:inst|counttemp[15] } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.590 ns) 1.857 ns phase_test:inst\|Equal0~174 2 COMB LC_X28_Y9_N2 1 " "Info: 2: + IC(1.267 ns) + CELL(0.590 ns) = 1.857 ns; Loc. = LC_X28_Y9_N2; Fanout = 1; COMB Node = 'phase_test:inst\|Equal0~174'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.857 ns" { phase_test:inst|counttemp[15] phase_test:inst|Equal0~174 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.590 ns) 2.874 ns phase_test:inst\|Equal0~176 3 COMB LC_X28_Y9_N1 1 " "Info: 3: + IC(0.427 ns) + CELL(0.590 ns) = 2.874 ns; Loc. = LC_X28_Y9_N1; Fanout = 1; COMB Node = 'phase_test:inst\|Equal0~176'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.017 ns" { phase_test:inst|Equal0~174 phase_test:inst|Equal0~176 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.189 ns) + CELL(0.442 ns) 4.505 ns phase_test:inst\|Equal0~179 4 COMB LC_X28_Y8_N1 4 " "Info: 4: + IC(1.189 ns) + CELL(0.442 ns) = 4.505 ns; Loc. = LC_X28_Y8_N1; Fanout = 4; COMB Node = 'phase_test:inst\|Equal0~179'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.631 ns" { phase_test:inst|Equal0~176 phase_test:inst|Equal0~179 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.197 ns) + CELL(0.423 ns) 6.125 ns phase_test:inst\|counttemp\[0\]~149 5 COMB LC_X27_Y9_N2 2 " "Info: 5: + IC(1.197 ns) + CELL(0.423 ns) = 6.125 ns; Loc. = LC_X27_Y9_N2; Fanout = 2; COMB Node = 'phase_test:inst\|counttemp\[0\]~149'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.620 ns" { phase_test:inst|Equal0~179 phase_test:inst|counttemp[0]~149 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 6.203 ns phase_test:inst\|counttemp\[1\]~145 6 COMB LC_X27_Y9_N3 2 " "Info: 6: + IC(0.000 ns) + CELL(0.078 ns) = 6.203 ns; Loc. = LC_X27_Y9_N3; Fanout = 2; COMB Node = 'phase_test:inst\|counttemp\[1\]~145'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { phase_test:inst|counttemp[0]~149 phase_test:inst|counttemp[1]~145 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 6.381 ns phase_test:inst\|counttemp\[2\]~148 7 COMB LC_X27_Y9_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.178 ns) = 6.381 ns; Loc. = LC_X27_Y9_N4; Fanout = 6; COMB Node = 'phase_test:inst\|counttemp\[2\]~148'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { phase_test:inst|counttemp[1]~145 phase_test:inst|counttemp[2]~148 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 6.589 ns phase_test:inst\|counttemp\[7\]~157 8 COMB LC_X27_Y9_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.208 ns) = 6.589 ns; Loc. = LC_X27_Y9_N9; Fanout = 6; COMB Node = 'phase_test:inst\|counttemp\[7\]~157'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { phase_test:inst|counttemp[2]~148 phase_test:inst|counttemp[7]~157 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 6.725 ns phase_test:inst\|counttemp\[12\]~155 9 COMB LC_X27_Y8_N4 3 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 6.725 ns; Loc. = LC_X27_Y8_N4; Fanout = 3; COMB Node = 'phase_test:inst\|counttemp\[12\]~155'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { phase_test:inst|counttemp[7]~157 phase_test:inst|counttemp[12]~155 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 7.564 ns phase_test:inst\|counttemp\[15\] 10 REG LC_X27_Y8_N7 2 " "Info: 10: + IC(0.000 ns) + CELL(0.839 ns) = 7.564 ns; Loc. = LC_X27_Y8_N7; Fanout = 2; REG Node = 'phase_test:inst\|counttemp\[15\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { phase_test:inst|counttemp[12]~155 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.484 ns ( 46.06 % ) " "Info: Total cell delay = 3.484 ns ( 46.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.080 ns ( 53.94 % ) " "Info: Total interconnect delay = 4.080 ns ( 53.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.564 ns" { phase_test:inst|counttemp[15] phase_test:inst|Equal0~174 phase_test:inst|Equal0~176 phase_test:inst|Equal0~179 phase_test:inst|counttemp[0]~149 phase_test:inst|counttemp[1]~145 phase_test:inst|counttemp[2]~148 phase_test:inst|counttemp[7]~157 phase_test:inst|counttemp[12]~155 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.564 ns" { phase_test:inst|counttemp[15] phase_test:inst|Equal0~174 phase_test:inst|Equal0~176 phase_test:inst|Equal0~179 phase_test:inst|counttemp[0]~149 phase_test:inst|counttemp[1]~145 phase_test:inst|counttemp[2]~148 phase_test:inst|counttemp[7]~157 phase_test:inst|counttemp[12]~155 phase_test:inst|counttemp[15] } { 0.000ns 1.267ns 0.427ns 1.189ns 1.197ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.423ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "phaseinA destination 7.766 ns + Shortest register " "Info: + Shortest clock path from clock \"phaseinA\" to destination register is 7.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns phaseinA 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'phaseinA'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phaseinA } "NODE_NAME" } } { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 136 -352 -184 152 "phaseinA" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.496 ns) + CELL(0.114 ns) 3.079 ns inst10 2 COMB LC_X8_Y13_N2 49 " "Info: 2: + IC(1.496 ns) + CELL(0.114 ns) = 3.079 ns; Loc. = LC_X8_Y13_N2; Fanout = 49; COMB Node = 'inst10'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.610 ns" { phaseinA inst10 } "NODE_NAME" } } { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 128 -160 -96 176 "inst10" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.976 ns) + CELL(0.711 ns) 7.766 ns phase_test:inst\|counttemp\[15\] 3 REG LC_X27_Y8_N7 2 " "Info: 3: + IC(3.976 ns) + CELL(0.711 ns) = 7.766 ns; Loc. = LC_X27_Y8_N7; Fanout = 2; REG Node = 'phase_test:inst\|counttemp\[15\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.687 ns" { inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.294 ns ( 29.54 % ) " "Info: Total cell delay = 2.294 ns ( 29.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.472 ns ( 70.46 % ) " "Info: Total interconnect delay = 5.472 ns ( 70.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.766 ns" { phaseinA inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.766 ns" { phaseinA phaseinA~out0 inst10 phase_test:inst|counttemp[15] } { 0.000ns 0.000ns 1.496ns 3.976ns } { 0.000ns 1.469ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "phaseinA source 7.766 ns - Longest register " "Info: - Longest clock path from clock \"phaseinA\" to source register is 7.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns phaseinA 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'phaseinA'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phaseinA } "NODE_NAME" } } { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 136 -352 -184 152 "phaseinA" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.496 ns) + CELL(0.114 ns) 3.079 ns inst10 2 COMB LC_X8_Y13_N2 49 " "Info: 2: + IC(1.496 ns) + CELL(0.114 ns) = 3.079 ns; Loc. = LC_X8_Y13_N2; Fanout = 49; COMB Node = 'inst10'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.610 ns" { phaseinA inst10 } "NODE_NAME" } } { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 128 -160 -96 176 "inst10" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.976 ns) + CELL(0.711 ns) 7.766 ns phase_test:inst\|counttemp\[15\] 3 REG LC_X27_Y8_N7 2 " "Info: 3: + IC(3.976 ns) + CELL(0.711 ns) = 7.766 ns; Loc. = LC_X27_Y8_N7; Fanout = 2; REG Node = 'phase_test:inst\|counttemp\[15\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.687 ns" { inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.294 ns ( 29.54 % ) " "Info: Total cell delay = 2.294 ns ( 29.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.472 ns ( 70.46 % ) " "Info: Total interconnect delay = 5.472 ns ( 70.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.766 ns" { phaseinA inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.766 ns" { phaseinA phaseinA~out0 inst10 phase_test:inst|counttemp[15] } { 0.000ns 0.000ns 1.496ns 3.976ns } { 0.000ns 1.469ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.766 ns" { phaseinA inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.766 ns" { phaseinA phaseinA~out0 inst10 phase_test:inst|counttemp[15] } { 0.000ns 0.000ns 1.496ns 3.976ns } { 0.000ns 1.469ns 0.114ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.766 ns" { phaseinA inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.766 ns" { phaseinA phaseinA~out0 inst10 phase_test:inst|counttemp[15] } { 0.000ns 0.000ns 1.496ns 3.976ns } { 0.000ns 1.469ns 0.114ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.564 ns" { phase_test:inst|counttemp[15] phase_test:inst|Equal0~174 phase_test:inst|Equal0~176 phase_test:inst|Equal0~179 phase_test:inst|counttemp[0]~149 phase_test:inst|counttemp[1]~145 phase_test:inst|counttemp[2]~148 phase_test:inst|counttemp[7]~157 phase_test:inst|counttemp[12]~155 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.564 ns" { phase_test:inst|counttemp[15] phase_test:inst|Equal0~174 phase_test:inst|Equal0~176 phase_test:inst|Equal0~179 phase_test:inst|counttemp[0]~149 phase_test:inst|counttemp[1]~145 phase_test:inst|counttemp[2]~148 phase_test:inst|counttemp[7]~157 phase_test:inst|counttemp[12]~155 phase_test:inst|counttemp[15] } { 0.000ns 1.267ns 0.427ns 1.189ns 1.197ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.423ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.766 ns" { phaseinA inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.766 ns" { phaseinA phaseinA~out0 inst10 phase_test:inst|counttemp[15] } { 0.000ns 0.000ns 1.496ns 3.976ns } { 0.000ns 1.469ns 0.114ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.766 ns" { phaseinA inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.766 ns" { phaseinA phaseinA~out0 inst10 phase_test:inst|counttemp[15] } { 0.000ns 0.000ns 1.496ns 3.976ns } { 0.000ns 1.469ns 0.114ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "phaseinB register phase_test:inst\|counttemp\[15\] register phase_test:inst\|counttemp\[15\] 127.8 MHz 7.825 ns Internal " "Info: Clock \"phaseinB\" has Internal fmax of 127.8 MHz between source register \"phase_test:inst\|counttemp\[15\]\" and destination register \"phase_test:inst\|counttemp\[15\]\" (period= 7.825 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.564 ns + Longest register register " "Info: + Longest register to register delay is 7.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns phase_test:inst\|counttemp\[15\] 1 REG LC_X27_Y8_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y8_N7; Fanout = 2; REG Node = 'phase_test:inst\|counttemp\[15\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_test:inst|counttemp[15] } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.590 ns) 1.857 ns phase_test:inst\|Equal0~174 2 COMB LC_X28_Y9_N2 1 " "Info: 2: + IC(1.267 ns) + CELL(0.590 ns) = 1.857 ns; Loc. = LC_X28_Y9_N2; Fanout = 1; COMB Node = 'phase_test:inst\|Equal0~174'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.857 ns" { phase_test:inst|counttemp[15] phase_test:inst|Equal0~174 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.590 ns) 2.874 ns phase_test:inst\|Equal0~176 3 COMB LC_X28_Y9_N1 1 " "Info: 3: + IC(0.427 ns) + CELL(0.590 ns) = 2.874 ns; Loc. = LC_X28_Y9_N1; Fanout = 1; COMB Node = 'phase_test:inst\|Equal0~176'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.017 ns" { phase_test:inst|Equal0~174 phase_test:inst|Equal0~176 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.189 ns) + CELL(0.442 ns) 4.505 ns phase_test:inst\|Equal0~179 4 COMB LC_X28_Y8_N1 4 " "Info: 4: + IC(1.189 ns) + CELL(0.442 ns) = 4.505 ns; Loc. = LC_X28_Y8_N1; Fanout = 4; COMB Node = 'phase_test:inst\|Equal0~179'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.631 ns" { phase_test:inst|Equal0~176 phase_test:inst|Equal0~179 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.197 ns) + CELL(0.423 ns) 6.125 ns phase_test:inst\|counttemp\[0\]~149 5 COMB LC_X27_Y9_N2 2 " "Info: 5: + IC(1.197 ns) + CELL(0.423 ns) = 6.125 ns; Loc. = LC_X27_Y9_N2; Fanout = 2; COMB Node = 'phase_test:inst\|counttemp\[0\]~149'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.620 ns" { phase_test:inst|Equal0~179 phase_test:inst|counttemp[0]~149 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 6.203 ns phase_test:inst\|counttemp\[1\]~145 6 COMB LC_X27_Y9_N3 2 " "Info: 6: + IC(0.000 ns) + CELL(0.078 ns) = 6.203 ns; Loc. = LC_X27_Y9_N3; Fanout = 2; COMB Node = 'phase_test:inst\|counttemp\[1\]~145'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { phase_test:inst|counttemp[0]~149 phase_test:inst|counttemp[1]~145 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 6.381 ns phase_test:inst\|counttemp\[2\]~148 7 COMB LC_X27_Y9_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.178 ns) = 6.381 ns; Loc. = LC_X27_Y9_N4; Fanout = 6; COMB Node = 'phase_test:inst\|counttemp\[2\]~148'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { phase_test:inst|counttemp[1]~145 phase_test:inst|counttemp[2]~148 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 6.589 ns phase_test:inst\|counttemp\[7\]~157 8 COMB LC_X27_Y9_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.208 ns) = 6.589 ns; Loc. = LC_X27_Y9_N9; Fanout = 6; COMB Node = 'phase_test:inst\|counttemp\[7\]~157'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { phase_test:inst|counttemp[2]~148 phase_test:inst|counttemp[7]~157 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 6.725 ns phase_test:inst\|counttemp\[12\]~155 9 COMB LC_X27_Y8_N4 3 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 6.725 ns; Loc. = LC_X27_Y8_N4; Fanout = 3; COMB Node = 'phase_test:inst\|counttemp\[12\]~155'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { phase_test:inst|counttemp[7]~157 phase_test:inst|counttemp[12]~155 } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 7.564 ns phase_test:inst\|counttemp\[15\] 10 REG LC_X27_Y8_N7 2 " "Info: 10: + IC(0.000 ns) + CELL(0.839 ns) = 7.564 ns; Loc. = LC_X27_Y8_N7; Fanout = 2; REG Node = 'phase_test:inst\|counttemp\[15\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { phase_test:inst|counttemp[12]~155 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.484 ns ( 46.06 % ) " "Info: Total cell delay = 3.484 ns ( 46.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.080 ns ( 53.94 % ) " "Info: Total interconnect delay = 4.080 ns ( 53.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.564 ns" { phase_test:inst|counttemp[15] phase_test:inst|Equal0~174 phase_test:inst|Equal0~176 phase_test:inst|Equal0~179 phase_test:inst|counttemp[0]~149 phase_test:inst|counttemp[1]~145 phase_test:inst|counttemp[2]~148 phase_test:inst|counttemp[7]~157 phase_test:inst|counttemp[12]~155 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.564 ns" { phase_test:inst|counttemp[15] phase_test:inst|Equal0~174 phase_test:inst|Equal0~176 phase_test:inst|Equal0~179 phase_test:inst|counttemp[0]~149 phase_test:inst|counttemp[1]~145 phase_test:inst|counttemp[2]~148 phase_test:inst|counttemp[7]~157 phase_test:inst|counttemp[12]~155 phase_test:inst|counttemp[15] } { 0.000ns 1.267ns 0.427ns 1.189ns 1.197ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.423ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "phaseinB destination 8.195 ns + Shortest register " "Info: + Shortest clock path from clock \"phaseinB\" to destination register is 8.195 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns phaseinB 1 CLK PIN_227 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_227; Fanout = 1; CLK Node = 'phaseinB'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phaseinB } "NODE_NAME" } } { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 152 -352 -184 168 "phaseinB" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.741 ns) + CELL(0.292 ns) 3.508 ns inst10 2 COMB LC_X8_Y13_N2 49 " "Info: 2: + IC(1.741 ns) + CELL(0.292 ns) = 3.508 ns; Loc. = LC_X8_Y13_N2; Fanout = 49; COMB Node = 'inst10'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.033 ns" { phaseinB inst10 } "NODE_NAME" } } { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 128 -160 -96 176 "inst10" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.976 ns) + CELL(0.711 ns) 8.195 ns phase_test:inst\|counttemp\[15\] 3 REG LC_X27_Y8_N7 2 " "Info: 3: + IC(3.976 ns) + CELL(0.711 ns) = 8.195 ns; Loc. = LC_X27_Y8_N7; Fanout = 2; REG Node = 'phase_test:inst\|counttemp\[15\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.687 ns" { inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.478 ns ( 30.24 % ) " "Info: Total cell delay = 2.478 ns ( 30.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.717 ns ( 69.76 % ) " "Info: Total interconnect delay = 5.717 ns ( 69.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.195 ns" { phaseinB inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "8.195 ns" { phaseinB phaseinB~out0 inst10 phase_test:inst|counttemp[15] } { 0.000ns 0.000ns 1.741ns 3.976ns } { 0.000ns 1.475ns 0.292ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "phaseinB source 8.195 ns - Longest register " "Info: - Longest clock path from clock \"phaseinB\" to source register is 8.195 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns phaseinB 1 CLK PIN_227 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_227; Fanout = 1; CLK Node = 'phaseinB'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phaseinB } "NODE_NAME" } } { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 152 -352 -184 168 "phaseinB" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.741 ns) + CELL(0.292 ns) 3.508 ns inst10 2 COMB LC_X8_Y13_N2 49 " "Info: 2: + IC(1.741 ns) + CELL(0.292 ns) = 3.508 ns; Loc. = LC_X8_Y13_N2; Fanout = 49; COMB Node = 'inst10'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.033 ns" { phaseinB inst10 } "NODE_NAME" } } { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 128 -160 -96 176 "inst10" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.976 ns) + CELL(0.711 ns) 8.195 ns phase_test:inst\|counttemp\[15\] 3 REG LC_X27_Y8_N7 2 " "Info: 3: + IC(3.976 ns) + CELL(0.711 ns) = 8.195 ns; Loc. = LC_X27_Y8_N7; Fanout = 2; REG Node = 'phase_test:inst\|counttemp\[15\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.687 ns" { inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.478 ns ( 30.24 % ) " "Info: Total cell delay = 2.478 ns ( 30.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.717 ns ( 69.76 % ) " "Info: Total interconnect delay = 5.717 ns ( 69.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.195 ns" { phaseinB inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "8.195 ns" { phaseinB phaseinB~out0 inst10 phase_test:inst|counttemp[15] } { 0.000ns 0.000ns 1.741ns 3.976ns } { 0.000ns 1.475ns 0.292ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.195 ns" { phaseinB inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "8.195 ns" { phaseinB phaseinB~out0 inst10 phase_test:inst|counttemp[15] } { 0.000ns 0.000ns 1.741ns 3.976ns } { 0.000ns 1.475ns 0.292ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.195 ns" { phaseinB inst10 phase_test:inst|counttemp[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "8.195 ns" { phaseinB phaseinB~out0 inst10 phase_test:inst|counttemp[15] } { 0