📄 phase_test.tan.qmsg
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{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "phase_pll:inst12\|altpll:altpll_component\|_clk0 register phase_test:inst\|sclr register phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[6\] 4.53 ns " "Info: Slack time is 4.53 ns for clock \"phase_pll:inst12\|altpll:altpll_component\|_clk0\" between source register \"phase_test:inst\|sclr\" and destination register \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[6\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "7.297 ns + Largest register register " "Info: + Largest register to register requirement is 7.297 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "8.115 ns + " "Info: + Setup relationship between source and destination is 8.115 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 8.115 ns " "Info: + Latch edge is 8.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination phase_pll:inst12\|altpll:altpll_component\|_clk0 10.000 ns -1.885 ns 50 " "Info: Clock period of Destination clock \"phase_pll:inst12\|altpll:altpll_component\|_clk0\" is 10.000 ns with offset of -1.885 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.557 ns + Largest " "Info: + Largest clock skew is -0.557 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "phase_pll:inst12\|altpll:altpll_component\|_clk0 destination 2.385 ns + Shortest register " "Info: + Shortest clock path from clock \"phase_pll:inst12\|altpll:altpll_component\|_clk0\" to destination register is 2.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns phase_pll:inst12\|altpll:altpll_component\|_clk0 1 CLK PLL_1 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 32; CLK Node = 'phase_pll:inst12\|altpll:altpll_component\|_clk0'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_pll:inst12|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.711 ns) 2.385 ns phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[6\] 2 REG LC_X24_Y12_N0 4 " "Info: 2: + IC(1.674 ns) + CELL(0.711 ns) = 2.385 ns; Loc. = LC_X24_Y12_N0; Fanout = 4; REG Node = 'phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[6\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } "NODE_NAME" } } { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.81 % ) " "Info: Total cell delay = 0.711 ns ( 29.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.674 ns ( 70.19 % ) " "Info: Total interconnect delay = 1.674 ns ( 70.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.942 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 53 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 53; CLK Node = 'clk'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 128 -72 96 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns phase_test:inst\|sclr 2 REG LC_X27_Y10_N7 32 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X27_Y10_N7; Fanout = 32; REG Node = 'phase_test:inst\|sclr'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk phase_test:inst|sclr } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk phase_test:inst|sclr } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 phase_test:inst|sclr } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk phase_test:inst|sclr } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 phase_test:inst|sclr } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 19 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk phase_test:inst|sclr } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 phase_test:inst|sclr } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.767 ns - Longest register register " "Info: - Longest register to register delay is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns phase_test:inst\|sclr 1 REG LC_X27_Y10_N7 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y10_N7; Fanout = 32; REG Node = 'phase_test:inst\|sclr'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_test:inst|sclr } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.655 ns) + CELL(1.112 ns) 2.767 ns phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[6\] 2 REG LC_X24_Y12_N0 4 " "Info: 2: + IC(1.655 ns) + CELL(1.112 ns) = 2.767 ns; Loc. = LC_X24_Y12_N0; Fanout = 4; REG Node = 'phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[6\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.767 ns" { phase_test:inst|sclr phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } "NODE_NAME" } } { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.112 ns ( 40.19 % ) " "Info: Total cell delay = 1.112 ns ( 40.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.655 ns ( 59.81 % ) " "Info: Total interconnect delay = 1.655 ns ( 59.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.767 ns" { phase_test:inst|sclr phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.767 ns" { phase_test:inst|sclr phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } { 0.000ns 1.655ns } { 0.000ns 1.112ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk phase_test:inst|sclr } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 phase_test:inst|sclr } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.767 ns" { phase_test:inst|sclr phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.767 ns" { phase_test:inst|sclr phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] } { 0.000ns 1.655ns } { 0.000ns 1.112ns } } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[29\] register phase_test:inst\|COUNTNUM\[29\] 303 ps " "Info: Slack time is 303 ps for clock \"clk\" between source register \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[29\]\" and destination register \"phase_test:inst\|COUNTNUM\[29\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.181 ns + Largest register register " "Info: + Largest register to register requirement is 2.181 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "1.885 ns + " "Info: + Setup relationship between source and destination is 1.885 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 8.115 ns " "Info: - Launch edge is 8.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source phase_pll:inst12\|altpll:altpll_component\|_clk0 10.000 ns -1.885 ns 50 " "Info: Clock period of Source clock \"phase_pll:inst12\|altpll:altpll_component\|_clk0\" is 10.000 ns with offset of -1.885 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.557 ns + Largest " "Info: + Largest clock skew is 0.557 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.942 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 53 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 53; CLK Node = 'clk'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 128 -72 96 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns phase_test:inst\|COUNTNUM\[29\] 2 REG LC_X26_Y11_N9 1 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X26_Y11_N9; Fanout = 1; REG Node = 'phase_test:inst\|COUNTNUM\[29\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk phase_test:inst|COUNTNUM[29] } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 70 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk phase_test:inst|COUNTNUM[29] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 phase_test:inst|COUNTNUM[29] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "phase_pll:inst12\|altpll:altpll_component\|_clk0 source 2.385 ns - Longest register " "Info: - Longest clock path from clock \"phase_pll:inst12\|altpll:altpll_component\|_clk0\" to source register is 2.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns phase_pll:inst12\|altpll:altpll_component\|_clk0 1 CLK PLL_1 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 32; CLK Node = 'phase_pll:inst12\|altpll:altpll_component\|_clk0'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_pll:inst12|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.711 ns) 2.385 ns phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[29\] 2 REG LC_X24_Y10_N3 4 " "Info: 2: + IC(1.674 ns) + CELL(0.711 ns) = 2.385 ns; Loc. = LC_X24_Y10_N3; Fanout = 4; REG Node = 'phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[29\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] } "NODE_NAME" } } { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.81 % ) " "Info: Total cell delay = 0.711 ns ( 29.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.674 ns ( 70.19 % ) " "Info: Total interconnect delay = 1.674 ns ( 70.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk phase_test:inst|COUNTNUM[29] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 phase_test:inst|COUNTNUM[29] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 70 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk phase_test:inst|COUNTNUM[29] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 phase_test:inst|COUNTNUM[29] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.878 ns - Longest register register " "Info: - Longest register to register delay is 1.878 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[29\] 1 REG LC_X24_Y10_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y10_N3; Fanout = 4; REG Node = 'phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[29\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] } "NODE_NAME" } } { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.569 ns) + CELL(0.309 ns) 1.878 ns phase_test:inst\|COUNTNUM\[29\] 2 REG LC_X26_Y11_N9 1 " "Info: 2: + IC(1.569 ns) + CELL(0.309 ns) = 1.878 ns; Loc. = LC_X26_Y11_N9; Fanout = 1; REG Node = 'phase_test:inst\|COUNTNUM\[29\]'" { } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.878 ns" { phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] phase_test:inst|COUNTNUM[29] } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 70 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 16.45 % ) " "Info: Total cell delay = 0.309 ns ( 16.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.569 ns ( 83.55 % ) " "Info: Total interconnect delay = 1.569 ns ( 83.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.878 ns" { phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] phase_test:inst|COUNTNUM[29] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.878 ns" { phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] phase_test:inst|COUNTNUM[29] } { 0.000ns 1.569ns } { 0.000ns 0.309ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk phase_test:inst|COUNTNUM[29] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 phase_test:inst|COUNTNUM[29] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.385 ns" { phase_pll:inst12|altpll:altpll_component|_clk0 phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] } { 0.000ns 1.674ns } { 0.000ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.878 ns" { phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] phase_test:inst|COUNTNUM[29] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.878 ns" { phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] phase_test:inst|COUNTNUM[29] } { 0.000ns 1.569ns } { 0.000ns 0.309ns } } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
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