phase_test.tan.qmsg

verilog编写基于fpga的鉴相器模块

{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "phaseinA " "Info: Assuming node \"phaseinA\" is an undefined clock" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 136 -352 -184 152 "phaseinA" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phaseinA" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "phaseinB " "Info: Assuming node \"phaseinB\" is an undefined clock" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 152 -352 -184 168 "phaseinB" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phaseinB" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "inst10 " "Info: Detected gated clock \"inst10\" as buffer" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 128 -160 -96 176 "inst10" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "inst10" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}