phase_test.hier_info

verilog编写基于fpga的鉴相器模块

updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => cntr_2ii:auto_generated.sclr
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
data[12] => ~NO_FANOUT~
data[13] => ~NO_FANOUT~
data[14] => ~NO_FANOUT~
data[15] => ~NO_FANOUT~
data[16] => ~NO_FANOUT~
data[17] => ~NO_FANOUT~
data[18] => ~NO_FANOUT~
data[19] => ~NO_FANOUT~
data[20] => ~NO_FANOUT~
data[21] => ~NO_FANOUT~
data[22] => ~NO_FANOUT~
data[23] => ~NO_FANOUT~
data[24] => ~NO_FANOUT~
data[25] => ~NO_FANOUT~
data[26] => ~NO_FANOUT~
data[27] => ~NO_FANOUT~
data[28] => ~NO_FANOUT~
data[29] => ~NO_FANOUT~
data[30] => ~NO_FANOUT~
data[31] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_2ii:auto_generated.q[0]
q[1] <= cntr_2ii:auto_generated.q[1]
q[2] <= cntr_2ii:auto_generated.q[2]
q[3] <= cntr_2ii:auto_generated.q[3]
q[4] <= cntr_2ii:auto_generated.q[4]
q[5] <= cntr_2ii:auto_generated.q[5]
q[6] <= cntr_2ii:auto_generated.q[6]
q[7] <= cntr_2ii:auto_generated.q[7]
q[8] <= cntr_2ii:auto_generated.q[8]
q[9] <= cntr_2ii:auto_generated.q[9]
q[10] <= cntr_2ii:auto_generated.q[10]
q[11] <= cntr_2ii:auto_generated.q[11]
q[12] <= cntr_2ii:auto_generated.q[12]
q[13] <= cntr_2ii:auto_generated.q[13]
q[14] <= cntr_2ii:auto_generated.q[14]
q[15] <= cntr_2ii:auto_generated.q[15]
q[16] <= cntr_2ii:auto_generated.q[16]
q[17] <= cntr_2ii:auto_generated.q[17]
q[18] <= cntr_2ii:auto_generated.q[18]
q[19] <= cntr_2ii:auto_generated.q[19]
q[20] <= cntr_2ii:auto_generated.q[20]
q[21] <= cntr_2ii:auto_generated.q[21]
q[22] <= cntr_2ii:auto_generated.q[22]
q[23] <= cntr_2ii:auto_generated.q[23]
q[24] <= cntr_2ii:auto_generated.q[24]
q[25] <= cntr_2ii:auto_generated.q[25]
q[26] <= cntr_2ii:auto_generated.q[26]
q[27] <= cntr_2ii:auto_generated.q[27]
q[28] <= cntr_2ii:auto_generated.q[28]
q[29] <= cntr_2ii:auto_generated.q[29]
q[30] <= cntr_2ii:auto_generated.q[30]
q[31] <= cntr_2ii:auto_generated.q[31]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
clock => counter_cella13.CLK
clock => counter_cella14.CLK
clock => counter_cella15.CLK
clock => counter_cella16.CLK
clock => counter_cella17.CLK
clock => counter_cella18.CLK
clock => counter_cella19.CLK
clock => counter_cella20.CLK
clock => counter_cella21.CLK
clock => counter_cella22.CLK
clock => counter_cella23.CLK
clock => counter_cella24.CLK
clock => counter_cella25.CLK
clock => counter_cella26.CLK
clock => counter_cella27.CLK
clock => counter_cella28.CLK
clock => counter_cella29.CLK
clock => counter_cella30.CLK
clock => counter_cella31.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
cnt_en => counter_cella5.DATAB
cnt_en => counter_cella6.DATAB
cnt_en => counter_cella7.DATAB
cnt_en => counter_cella8.DATAB
cnt_en => counter_cella9.DATAB
cnt_en => counter_cella10.DATAB
cnt_en => counter_cella11.DATAB
cnt_en => counter_cella12.DATAB
cnt_en => counter_cella13.DATAB
cnt_en => counter_cella14.DATAB
cnt_en => counter_cella15.DATAB
cnt_en => counter_cella16.DATAB
cnt_en => counter_cella17.DATAB
cnt_en => counter_cella18.DATAB
cnt_en => counter_cella19.DATAB
cnt_en => counter_cella20.DATAB
cnt_en => counter_cella21.DATAB
cnt_en => counter_cella22.DATAB
cnt_en => counter_cella23.DATAB
cnt_en => counter_cella24.DATAB
cnt_en => counter_cella25.DATAB
cnt_en => counter_cella26.DATAB
cnt_en => counter_cella27.DATAB
cnt_en => counter_cella28.DATAB
cnt_en => counter_cella29.DATAB
cnt_en => counter_cella30.DATAB
cnt_en => counter_cella31.DATAB
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT
q[13] <= counter_cella13.REGOUT
q[14] <= counter_cella14.REGOUT
q[15] <= counter_cella15.REGOUT
q[16] <= counter_cella16.REGOUT
q[17] <= counter_cella17.REGOUT
q[18] <= counter_cella18.REGOUT
q[19] <= counter_cella19.REGOUT
q[20] <= counter_cella20.REGOUT
q[21] <= counter_cella21.REGOUT
q[22] <= counter_cella22.REGOUT
q[23] <= counter_cella23.REGOUT
q[24] <= counter_cella24.REGOUT
q[25] <= counter_cella25.REGOUT
q[26] <= counter_cella26.REGOUT
q[27] <= counter_cella27.REGOUT
q[28] <= counter_cella28.REGOUT
q[29] <= counter_cella29.REGOUT
q[30] <= counter_cella30.REGOUT
q[31] <= counter_cella31.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR
sclr => counter_cella4.SCLR
sclr => counter_cella5.SCLR
sclr => counter_cella6.SCLR
sclr => counter_cella7.SCLR
sclr => counter_cella8.SCLR
sclr => counter_cella9.SCLR
sclr => counter_cella10.SCLR
sclr => counter_cella11.SCLR
sclr => counter_cella12.SCLR
sclr => counter_cella13.SCLR
sclr => counter_cella14.SCLR
sclr => counter_cella15.SCLR
sclr => counter_cella16.SCLR
sclr => counter_cella17.SCLR
sclr => counter_cella18.SCLR
sclr => counter_cella19.SCLR
sclr => counter_cella20.SCLR
sclr => counter_cella21.SCLR
sclr => counter_cella22.SCLR
sclr => counter_cella23.SCLR
sclr => counter_cella24.SCLR
sclr => counter_cella25.SCLR
sclr => counter_cella26.SCLR
sclr => counter_cella27.SCLR
sclr => counter_cella28.SCLR
sclr => counter_cella29.SCLR
sclr => counter_cella30.SCLR
sclr => counter_cella31.SCLR


|phase_control|phase_pll:inst12
inclk0 => sub_wire3[0].IN1
pllena => pllena~0.IN1
c0 <= altpll:altpll_component.clk


|phase_control|phase_pll:inst12|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => pll.ENABLE
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => pll.ENA2
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= <UNC>
clk[2] <= pll.CLK2
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE