phase_test.hier_info

verilog编写基于fpga的鉴相器模块

|phase_control
phase_result[0] <= phase_test:inst.COUNTNUM[0]
phase_result[1] <= phase_test:inst.COUNTNUM[1]
phase_result[2] <= phase_test:inst.COUNTNUM[2]
phase_result[3] <= phase_test:inst.COUNTNUM[3]
phase_result[4] <= phase_test:inst.COUNTNUM[4]
phase_result[5] <= phase_test:inst.COUNTNUM[5]
phase_result[6] <= phase_test:inst.COUNTNUM[6]
phase_result[7] <= phase_test:inst.COUNTNUM[7]
phase_result[8] <= phase_test:inst.COUNTNUM[8]
phase_result[9] <= phase_test:inst.COUNTNUM[9]
phase_result[10] <= phase_test:inst.COUNTNUM[10]
phase_result[11] <= phase_test:inst.COUNTNUM[11]
phase_result[12] <= phase_test:inst.COUNTNUM[12]
phase_result[13] <= phase_test:inst.COUNTNUM[13]
phase_result[14] <= phase_test:inst.COUNTNUM[14]
phase_result[15] <= phase_test:inst.COUNTNUM[15]
phase_result[16] <= phase_test:inst.COUNTNUM[16]
phase_result[17] <= phase_test:inst.COUNTNUM[17]
phase_result[18] <= phase_test:inst.COUNTNUM[18]
phase_result[19] <= phase_test:inst.COUNTNUM[19]
phase_result[20] <= phase_test:inst.COUNTNUM[20]
phase_result[21] <= phase_test:inst.COUNTNUM[21]
phase_result[22] <= phase_test:inst.COUNTNUM[22]
phase_result[23] <= phase_test:inst.COUNTNUM[23]
phase_result[24] <= phase_test:inst.COUNTNUM[24]
phase_result[25] <= phase_test:inst.COUNTNUM[25]
phase_result[26] <= phase_test:inst.COUNTNUM[26]
phase_result[27] <= phase_test:inst.COUNTNUM[27]
phase_result[28] <= phase_test:inst.COUNTNUM[28]
phase_result[29] <= phase_test:inst.COUNTNUM[29]
phase_result[30] <= phase_test:inst.COUNTNUM[30]
phase_result[31] <= phase_test:inst.COUNTNUM[31]
clk => phase_test:inst.clk
clk => phase_pll:inst12.inclk0
phaseinA => inst10.IN0
phaseinB => inst10.IN1
cs_phase => phase_test:inst.cs
gatein[0] => phase_test:inst.gatein[0]
gatein[1] => phase_test:inst.gatein[1]
gatein[2] => phase_test:inst.gatein[2]
gatein[3] => phase_test:inst.gatein[3]
gatein[4] => phase_test:inst.gatein[4]
gatein[5] => phase_test:inst.gatein[5]
gatein[6] => phase_test:inst.gatein[6]
gatein[7] => phase_test:inst.gatein[7]
gatein[8] => phase_test:inst.gatein[8]
gatein[9] => phase_test:inst.gatein[9]
gatein[10] => phase_test:inst.gatein[10]
gatein[11] => phase_test:inst.gatein[11]
gatein[12] => phase_test:inst.gatein[12]
gatein[13] => phase_test:inst.gatein[13]
gatein[14] => phase_test:inst.gatein[14]
gatein[15] => phase_test:inst.gatein[15]
phase_sig[0] => phase_test:inst.phase_sig[0]
phase_sig[1] => phase_test:inst.phase_sig[1]


|phase_control|phase_test:inst
clk => gatelim[15].CLK
clk => gatelim[14].CLK
clk => gatelim[13].CLK
clk => gatelim[12].CLK
clk => gatelim[11].CLK
clk => gatelim[10].CLK
clk => gatelim[9].CLK
clk => gatelim[8].CLK
clk => gatelim[7].CLK
clk => gatelim[6].CLK
clk => gatelim[5].CLK
clk => gatelim[4].CLK
clk => gatelim[3].CLK
clk => gatelim[2].CLK
clk => gatelim[1].CLK
clk => gatelim[0].CLK
clk => countstart.CLK
clk => PLLEN~reg0.CLK
clk => sclr~reg0.CLK
clk => COUNTNUM[31]~reg0.CLK
clk => COUNTNUM[30]~reg0.CLK
clk => COUNTNUM[29]~reg0.CLK
clk => COUNTNUM[28]~reg0.CLK
clk => COUNTNUM[27]~reg0.CLK
clk => COUNTNUM[26]~reg0.CLK
clk => COUNTNUM[25]~reg0.CLK
clk => COUNTNUM[24]~reg0.CLK
clk => COUNTNUM[23]~reg0.CLK
clk => COUNTNUM[22]~reg0.CLK
clk => COUNTNUM[21]~reg0.CLK
clk => COUNTNUM[20]~reg0.CLK
clk => COUNTNUM[19]~reg0.CLK
clk => COUNTNUM[18]~reg0.CLK
clk => COUNTNUM[17]~reg0.CLK
clk => COUNTNUM[16]~reg0.CLK
clk => COUNTNUM[15]~reg0.CLK
clk => COUNTNUM[14]~reg0.CLK
clk => COUNTNUM[13]~reg0.CLK
clk => COUNTNUM[12]~reg0.CLK
clk => COUNTNUM[11]~reg0.CLK
clk => COUNTNUM[10]~reg0.CLK
clk => COUNTNUM[9]~reg0.CLK
clk => COUNTNUM[8]~reg0.CLK
clk => COUNTNUM[7]~reg0.CLK
clk => COUNTNUM[6]~reg0.CLK
clk => COUNTNUM[5]~reg0.CLK
clk => COUNTNUM[4]~reg0.CLK
clk => COUNTNUM[3]~reg0.CLK
clk => COUNTNUM[2]~reg0.CLK
clk => COUNTNUM[1]~reg0.CLK
clk => COUNTNUM[0]~reg0.CLK
clk => state~5.IN1
combphasein => counttemp[15].CLK
combphasein => counttemp[14].CLK
combphasein => counttemp[13].CLK
combphasein => counttemp[12].CLK
combphasein => counttemp[11].CLK
combphasein => counttemp[10].CLK
combphasein => counttemp[9].CLK
combphasein => counttemp[8].CLK
combphasein => counttemp[7].CLK
combphasein => counttemp[6].CLK
combphasein => counttemp[5].CLK
combphasein => counttemp[4].CLK
combphasein => counttemp[3].CLK
combphasein => counttemp[2].CLK
combphasein => counttemp[1].CLK
combphasein => counttemp[0].CLK
combphasein => countstop.CLK
cs => state~3.OUTPUTSELECT
cs => state~4.OUTPUTSELECT
cs => gatelim~32.OUTPUTSELECT
cs => gatelim~33.OUTPUTSELECT
cs => gatelim~34.OUTPUTSELECT
cs => gatelim~35.OUTPUTSELECT
cs => gatelim~36.OUTPUTSELECT
cs => gatelim~37.OUTPUTSELECT
cs => gatelim~38.OUTPUTSELECT
cs => gatelim~39.OUTPUTSELECT
cs => gatelim~40.OUTPUTSELECT
cs => gatelim~41.OUTPUTSELECT
cs => gatelim~42.OUTPUTSELECT
cs => gatelim~43.OUTPUTSELECT
cs => gatelim~44.OUTPUTSELECT
cs => gatelim~45.OUTPUTSELECT
cs => gatelim~46.OUTPUTSELECT
cs => gatelim~47.OUTPUTSELECT
cs => countstart~2.OUTPUTSELECT
cs => PLLEN~3.OUTPUTSELECT
cs => sclr~reg0.ENA
phase_sig[0] => Decoder0.IN1
phase_sig[1] => Decoder0.IN0
gatein[0] => gatelim~15.DATAB
gatein[1] => gatelim~14.DATAB
gatein[2] => gatelim~13.DATAB
gatein[3] => gatelim~12.DATAB
gatein[4] => gatelim~11.DATAB
gatein[5] => gatelim~10.DATAB
gatein[6] => gatelim~9.DATAB
gatein[7] => gatelim~8.DATAB
gatein[8] => gatelim~7.DATAB
gatein[9] => gatelim~6.DATAB
gatein[10] => gatelim~5.DATAB
gatein[11] => gatelim~4.DATAB
gatein[12] => gatelim~3.DATAB
gatein[13] => gatelim~2.DATAB
gatein[14] => gatelim~1.DATAB
gatein[15] => gatelim~0.DATAB
clkcountin[0] => COUNTNUM[0]~reg0.DATAIN
clkcountin[1] => COUNTNUM[1]~reg0.DATAIN
clkcountin[2] => COUNTNUM[2]~reg0.DATAIN
clkcountin[3] => COUNTNUM[3]~reg0.DATAIN
clkcountin[4] => COUNTNUM[4]~reg0.DATAIN
clkcountin[5] => COUNTNUM[5]~reg0.DATAIN
clkcountin[6] => COUNTNUM[6]~reg0.DATAIN
clkcountin[7] => COUNTNUM[7]~reg0.DATAIN
clkcountin[8] => COUNTNUM[8]~reg0.DATAIN
clkcountin[9] => COUNTNUM[9]~reg0.DATAIN
clkcountin[10] => COUNTNUM[10]~reg0.DATAIN
clkcountin[11] => COUNTNUM[11]~reg0.DATAIN
clkcountin[12] => COUNTNUM[12]~reg0.DATAIN
clkcountin[13] => COUNTNUM[13]~reg0.DATAIN
clkcountin[14] => COUNTNUM[14]~reg0.DATAIN
clkcountin[15] => COUNTNUM[15]~reg0.DATAIN
clkcountin[16] => COUNTNUM[16]~reg0.DATAIN
clkcountin[17] => COUNTNUM[17]~reg0.DATAIN
clkcountin[18] => COUNTNUM[18]~reg0.DATAIN
clkcountin[19] => COUNTNUM[19]~reg0.DATAIN
clkcountin[20] => COUNTNUM[20]~reg0.DATAIN
clkcountin[21] => COUNTNUM[21]~reg0.DATAIN
clkcountin[22] => COUNTNUM[22]~reg0.DATAIN
clkcountin[23] => COUNTNUM[23]~reg0.DATAIN
clkcountin[24] => COUNTNUM[24]~reg0.DATAIN
clkcountin[25] => COUNTNUM[25]~reg0.DATAIN
clkcountin[26] => COUNTNUM[26]~reg0.DATAIN
clkcountin[27] => COUNTNUM[27]~reg0.DATAIN
clkcountin[28] => COUNTNUM[28]~reg0.DATAIN
clkcountin[29] => COUNTNUM[29]~reg0.DATAIN
clkcountin[30] => COUNTNUM[30]~reg0.DATAIN
clkcountin[31] => COUNTNUM[31]~reg0.DATAIN
COUNTNUM[0] <= COUNTNUM[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[1] <= COUNTNUM[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[2] <= COUNTNUM[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[3] <= COUNTNUM[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[4] <= COUNTNUM[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[5] <= COUNTNUM[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[6] <= COUNTNUM[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[7] <= COUNTNUM[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[8] <= COUNTNUM[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[9] <= COUNTNUM[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[10] <= COUNTNUM[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[11] <= COUNTNUM[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[12] <= COUNTNUM[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[13] <= COUNTNUM[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[14] <= COUNTNUM[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[15] <= COUNTNUM[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[16] <= COUNTNUM[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[17] <= COUNTNUM[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[18] <= COUNTNUM[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[19] <= COUNTNUM[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[20] <= COUNTNUM[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[21] <= COUNTNUM[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[22] <= COUNTNUM[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[23] <= COUNTNUM[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[24] <= COUNTNUM[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[25] <= COUNTNUM[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[26] <= COUNTNUM[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[27] <= COUNTNUM[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[28] <= COUNTNUM[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[29] <= COUNTNUM[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[30] <= COUNTNUM[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNTNUM[31] <= COUNTNUM[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sclr <= sclr~reg0.DB_MAX_OUTPUT_PORT_TYPE
PLLEN <= PLLEN~reg0.DB_MAX_OUTPUT_PORT_TYPE


|phase_control|phase_counter:inst1
clock => clock~0.IN1
cnt_en => cnt_en~0.IN1
sclr => sclr~0.IN1
q[0] <= lpm_counter:lpm_counter_component.q
q[1] <= lpm_counter:lpm_counter_component.q
q[2] <= lpm_counter:lpm_counter_component.q
q[3] <= lpm_counter:lpm_counter_component.q
q[4] <= lpm_counter:lpm_counter_component.q
q[5] <= lpm_counter:lpm_counter_component.q
q[6] <= lpm_counter:lpm_counter_component.q
q[7] <= lpm_counter:lpm_counter_component.q
q[8] <= lpm_counter:lpm_counter_component.q
q[9] <= lpm_counter:lpm_counter_component.q
q[10] <= lpm_counter:lpm_counter_component.q
q[11] <= lpm_counter:lpm_counter_component.q
q[12] <= lpm_counter:lpm_counter_component.q
q[13] <= lpm_counter:lpm_counter_component.q
q[14] <= lpm_counter:lpm_counter_component.q
q[15] <= lpm_counter:lpm_counter_component.q
q[16] <= lpm_counter:lpm_counter_component.q
q[17] <= lpm_counter:lpm_counter_component.q
q[18] <= lpm_counter:lpm_counter_component.q
q[19] <= lpm_counter:lpm_counter_component.q
q[20] <= lpm_counter:lpm_counter_component.q
q[21] <= lpm_counter:lpm_counter_component.q
q[22] <= lpm_counter:lpm_counter_component.q
q[23] <= lpm_counter:lpm_counter_component.q
q[24] <= lpm_counter:lpm_counter_component.q
q[25] <= lpm_counter:lpm_counter_component.q
q[26] <= lpm_counter:lpm_counter_component.q
q[27] <= lpm_counter:lpm_counter_component.q
q[28] <= lpm_counter:lpm_counter_component.q
q[29] <= lpm_counter:lpm_counter_component.q
q[30] <= lpm_counter:lpm_counter_component.q
q[31] <= lpm_counter:lpm_counter_component.q


|phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component
clock => cntr_2ii:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => cntr_2ii:auto_generated.cnt_en