phase_test.map.qmsg

verilog编写基于fpga的鉴相器模块

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 19 20:48:56 2007 " "Info: Processing started: Sun Aug 19 20:48:56 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off phase_test -c phase_test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off phase_test -c phase_test" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../phase_test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../phase_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 phase_test " "Info: Found entity 1: phase_test" {  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../phase_control.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../phase_control.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 phase_control " "Info: Found entity 1: phase_control" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "phase_control " "Info: Elaborating entity \"phase_control\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "phase_test phase_test:inst " "Info: Elaborating entity \"phase_test\" for hierarchy \"phase_test:inst\"" {  } { { "../phase_control.bdf" "inst" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 104 160 392 264 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "phase_test.v(45) " "Info (10264): Verilog HDL Case Statement information at phase_test.v(45): all case item expressions in this case statement are onehot" {  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 45 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 phase_test.v(83) " "Warning (10230): Verilog HDL assignment warning at phase_test.v(83): truncated value with size 32 to match size of target (16)" {  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "phase_counter.v 1 1 " "Warning: Using design file phase_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 phase_counter " "Info: Found entity 1: phase_counter" {  } { { "phase_counter.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/phase_counter.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "phase_counter phase_counter:inst1 " "Info: Elaborating entity \"phase_counter\" for hierarchy \"phase_counter:inst1\"" {  } { { "../phase_control.bdf" "inst1" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 120 488 632 248 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter phase_counter:inst1\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"phase_counter:inst1\|lpm_counter:lpm_counter_component\"" {  } { { "phase_counter.v" "lpm_counter_component" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/phase_counter.v" 65 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "phase_counter:inst1\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"phase_counter:inst1\|lpm_counter:lpm_counter_component\"" {  } { { "phase_counter.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/phase_counter.v" 65 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_2ii.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_2ii.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_2ii " "Info: Found entity 1: cntr_2ii" {  } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_2ii phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated " "Info: Elaborating entity \"cntr_2ii\" for hierarchy \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "phase_pll.v 1 1 " "Warning: Using design file phase_pll.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 phase_pll " "Info: Found entity 1: phase_pll" {  } { { "phase_pll.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/phase_pll.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "phase_pll phase_pll:inst12 " "Info: Elaborating entity \"phase_pll\" for hierarchy \"phase_pll:inst12\"" {  } { { "../phase_control.bdf" "inst12" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { -120 136 376 40 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/quartus60/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll phase_pll:inst12\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"phase_pll:inst12\|altpll:altpll_component\"" {  } { { "phase_pll.v" "altpll_component" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/phase_pll.v" 77 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "phase_pll:inst12\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"phase_pll:inst12\|altpll:altpll_component\"" {  } { { "phase_pll.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/phase_pll.v" 77 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|phase_control\|phase_test:inst\|state 2 " "Info: State machine \"\|phase_control\|phase_test:inst\|state\" contains 2 states" {  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 27 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|phase_control\|phase_test:inst\|state " "Info: Selected Auto state machine encoding method for state machine \"\|phase_control\|phase_test:inst\|state\"" {  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 27 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|phase_control\|phase_test:inst\|state " "Info: Encoding result for state machine \"\|phase_control\|phase_test:inst\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "1 " "Info: Completed encoding using 1 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "phase_test:inst\|state.COUNT " "Info: Encoded state bit \"phase_test:inst\|state.COUNT\"" {  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|phase_control\|phase_test:inst\|state.IDLE 0 " "Info: State \"\|phase_control\|phase_test:inst\|state.IDLE\" uses code string \"0\"" {  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|phase_control\|phase_test:inst\|state.COUNT 1 " "Info: State \"\|phase_control\|phase_test:inst\|state.COUNT\" uses code string \"1\"" {  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 27 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "173 " "Info: Implemented 173 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "22 " "Info: Implemented 22 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "118 " "Info: Implemented 118 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 19 20:48:59 2007 " "Info: Processing ended: Sun Aug 19 20:48:59 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}