phase_test.fit.qmsg

verilog编写基于fpga的鉴相器模块

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.883 ns register register " "Info: Estimated most critical path is register to register delay of 1.883 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[30\] 1 REG LAB_X24_Y10 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X24_Y10; Fanout = 3; REG Node = 'phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|safe_q\[30\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[30] } "NODE_NAME" } } { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.145 ns) + CELL(0.738 ns) 1.883 ns phase_test:inst\|COUNTNUM\[30\] 2 REG LAB_X26_Y11 1 " "Info: 2: + IC(1.145 ns) + CELL(0.738 ns) = 1.883 ns; Loc. = LAB_X26_Y11; Fanout = 1; REG Node = 'phase_test:inst\|COUNTNUM\[30\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.883 ns" { phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[30] phase_test:inst|COUNTNUM[30] } "NODE_NAME" } } { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 39.19 % ) " "Info: Total cell delay = 0.738 ns ( 39.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 60.81 % ) " "Info: Total interconnect delay = 1.145 ns ( 60.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.883 ns" { phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[30] phase_test:inst|COUNTNUM[30] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x24_y11 x35_y21 " "Info: The peak interconnect region extends from location x24_y11 to location x35_y21" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interc