phase_test.fit.qmsg

verilog编写基于fpga的鉴相器模块

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "inst10 Global clock " "Info: Automatically promoted some destinations of signal \"inst10\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella31 " "Info: Destination \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella31\" may be non-global or may not use global clock" {  } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella30 " "Info: Destination \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella30\" may be non-global or may not use global clock" {  } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella29 " "Info: Destination \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella29\" may be non-global or may not use global clock" {  } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella28 " "Info: Destination \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella28\" may be non-global or may not use global clock" {  } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella27 " "Info: Destination \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella27\" may be non-global or may not use global clock" {  } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella26 " "Info: Destination \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella26\" may be non-global or may not use global clock" {  } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella25 " "Info: Destination \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella25\" may be non-global or may not use global clock" {  } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella24 " "Info: Destination \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella24\" may be non-global or may not use global clock" {  } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella23 " "Info: Destination \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella23\" may be non-global or may not use global clock" {  } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella22 " "Info: Destination \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\|counter_cella22\" may be non-global or may not use global clock" {  } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 293 8 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 128 -160 -96 176 "inst10" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}