phase_test.fit.qmsg

verilog编写基于fpga的鉴相器模块

{ "Info" "IFIOMGR_PINS_MISSING_LOCATION_INFO" "54 54 " "Info: No exact pin location assignment(s) for 54 pins of 54 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[31\] " "Info: Pin phase_result\[31\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[31\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[31] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[30\] " "Info: Pin phase_result\[30\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[30\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[30] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[29\] " "Info: Pin phase_result\[29\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[29\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[29] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[28\] " "Info: Pin phase_result\[28\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[28\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[28] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[27\] " "Info: Pin phase_result\[27\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[27\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[27] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[26\] " "Info: Pin phase_result\[26\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[26\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[26] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[25\] " "Info: Pin phase_result\[25\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[25\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[25] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[24\] " "Info: Pin phase_result\[24\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[24\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[24] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[23\] " "Info: Pin phase_result\[23\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[23\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[23] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[22\] " "Info: Pin phase_result\[22\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[22\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[22] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[21\] " "Info: Pin phase_result\[21\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[21\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[21] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[20\] " "Info: Pin phase_result\[20\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[20\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[20] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[19\] " "Info: Pin phase_result\[19\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[19\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[19] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[18\] " "Info: Pin phase_result\[18\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[18\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[18] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[17\] " "Info: Pin phase_result\[17\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[17\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[17] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[16\] " "Info: Pin phase_result\[16\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[16\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[16] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[15\] " "Info: Pin phase_result\[15\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[15\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[14\] " "Info: Pin phase_result\[14\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[14\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[14] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[13\] " "Info: Pin phase_result\[13\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[13\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[13] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[12\] " "Info: Pin phase_result\[12\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[12\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[12] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[11\] " "Info: Pin phase_result\[11\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[11\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[11] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[10\] " "Info: Pin phase_result\[10\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[10\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[10] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[9\] " "Info: Pin phase_result\[9\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[9\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[9] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[8\] " "Info: Pin phase_result\[8\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[8\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[8] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[7\] " "Info: Pin phase_result\[7\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[7\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[6\] " "Info: Pin phase_result\[6\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[6\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[6] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[5\] " "Info: Pin phase_result\[5\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[5\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[4\] " "Info: Pin phase_result\[4\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[4\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[4] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[3\] " "Info: Pin phase_result\[3\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[3\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[3] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[2\] " "Info: Pin phase_result\[2\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[2\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[1\] " "Info: Pin phase_result\[1\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[1\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_result\[0\] " "Info: Pin phase_result\[0\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 80 648 837 96 "phase_result\[31..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_result\[0\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_result[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 128 -72 96 144 "clk" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cs_phase " "Info: Pin cs_phase not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 160 -72 96 176 "cs_phase" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cs_phase" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cs_phase } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cs_phase } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phaseinA " "Info: Pin phaseinA not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 136 -352 -184 152 "phaseinA" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phaseinA" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phaseinA } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phaseinA } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phaseinB " "Info: Pin phaseinB not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 152 -352 -184 168 "phaseinB" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phaseinB" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phaseinB } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phaseinB } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_sig\[1\] " "Info: Pin phase_sig\[1\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 176 -72 96 192 "phase_sig\[1..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_sig\[1\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_sig[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_sig[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "phase_sig\[0\] " "Info: Pin phase_sig\[0\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 176 -72 96 192 "phase_sig\[1..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_sig\[0\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_sig[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_sig[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[1\] " "Info: Pin gatein\[1\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[1\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[4\] " "Info: Pin gatein\[4\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[4\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[4] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[8\] " "Info: Pin gatein\[8\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[8\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[8] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[9\] " "Info: Pin gatein\[9\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[9\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[9] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[0\] " "Info: Pin gatein\[0\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[0\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[2\] " "Info: Pin gatein\[2\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[2\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[10\] " "Info: Pin gatein\[10\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[10\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[10] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[11\] " "Info: Pin gatein\[11\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[11\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[11] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[15\] " "Info: Pin gatein\[15\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[15\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[15] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[3\] " "Info: Pin gatein\[3\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[3\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[3] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[5\] " "Info: Pin gatein\[5\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[5\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[12\] " "Info: Pin gatein\[12\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[12\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[12] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[7\] " "Info: Pin gatein\[7\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[7\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[13\] " "Info: Pin gatein\[13\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[13\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[13] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[6\] " "Info: Pin gatein\[6\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[6\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[6] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "gatein\[14\] " "Info: Pin gatein\[14\] not assigned to an exact location on the device" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 192 -72 96 208 "gatein\[15..0\]" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gatein\[14\]" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[14] } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gatein[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "clk " "Info: Promoted signal \"clk\" to use global clock" {  } { { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } { 0 "clk" } } } } { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 128 -72 96 144 "clk" "" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "phase_pll:inst12\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"phase_pll:inst12\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "phase_pll:inst12\|altpll:altpll_component\|_clk0" } { 0 "phase_pll:inst12\|altpll:altpll_component\|_clk0" } } } } { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { -120 136 376 40 "inst12" "" } } } } { "altpll.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_pll:inst12|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phase_pll:inst12|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}