📄 phase_test.vwf

📁 verilog编写基于fpga的鉴相器模块
💻 VWF
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SIGNAL("count_gatein[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "count_gatein";
}

SIGNAL("count_gatein[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "count_gatein";
}

SIGNAL("count_gatein[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "count_gatein";
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10000;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 10.0;
		}
	}
}

TRANSITION_LIST("cs_phase")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 199960.0;
	}
}

TRANSITION_LIST("gatein[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("gatein[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("gatein[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("gatein[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("gatein[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("gatein[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("gatein[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("gatein[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("gatein[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("gatein[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 130.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 199850.0;
	}
}

TRANSITION_LIST("gatein[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 130.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 199850.0;
	}
}

TRANSITION_LIST("gatein[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("gatein[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("gatein[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 130.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 199850.0;
	}
}

TRANSITION_LIST("gatein[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("gatein[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[31]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[30]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[29]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[28]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[27]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[26]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[25]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[24]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[23]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[22]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[21]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[20]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[19]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[18]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[17]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[16]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 50037.814;
		LEVEL 1 FOR 149962.186;
	}
}

TRANSITION_LIST("phase_result[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 50037.763;
		LEVEL 1 FOR 149962.237;
	}
}

TRANSITION_LIST("phase_result[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 50037.18;
		LEVEL 1 FOR 149962.82;
	}
}

TRANSITION_LIST("phase_result[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phase_result[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("phaseinA")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 500.0;
		LEVEL 1 FOR 500.0;
		NODE
		{
			REPEAT = 199;
			LEVEL 0 FOR 500.0;
			LEVEL 1 FOR 500.0;
		}
	}
}

TRANSITION_LIST("phaseinB")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 20.0;
		NODE
		{
			REPEAT = 199;
			LEVEL 0 FOR 500.0;
			LEVEL 1 FOR 500.0;
		}
		LEVEL 0 FOR 500.0;
		LEVEL 1 FOR 480.0;
	}
}

TRANSITION_LIST("phase_sig[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 199930.0;
	}
}

TRANSITION_LIST("phase_sig[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 130.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 199850.0;
	}
}

TRANSITION_LIST("count_gatein[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("count_gatein[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("count_gatein[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("count_gatein[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("count_gatein[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("count_gatein[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("count_gatein[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("count_gatein[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("count_gatein[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 200000.0;
	}
}

TRANSITION_LIST("count_gatein[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 31528.419;
		LEVEL 1 FOR 19000.0;
		LEVEL 0 FOR 149471.581;
	}
}

TRANSITION_LIST("count_gatein[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 15528.419;
		LEVEL 1 FOR 16000.0;
		LEVEL 0 FOR 16000.0;
		LEVEL 1 FOR 3000.0;
		LEVEL 0 FOR 149471.581;
	}
}

TRANSITION_LIST("count_gatein[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 7528.419;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 8000.0;
			LEVEL 0 FOR 8000.0;
		}
		LEVEL 1 FOR 8000.0;
		LEVEL 0 FOR 152471.581;
	}
}

TRANSITION_LIST("count_gatein[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3528.419;
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 4000.0;
			LEVEL 0 FOR 4000.0;
		}
		LEVEL 1 FOR 4000.0;
		LEVEL 0 FOR 152471.581;
	}
}

TRANSITION_LIST("count_gatein[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1528.419;
		NODE
		{
			REPEAT = 12;
			LEVEL 1 FOR 2000.0;
			LEVEL 0 FOR 2000.0;
		}
		LEVEL 1 FOR 1000.0;
		LEVEL 0 FOR 149471.581;
	}
}

TRANSITION_LIST("count_gatein[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 528.419;
		NODE
		{
			REPEAT = 24;
			LEVEL 1 FOR 1000.0;
			LEVEL 0 FOR 1000.0;
		}
		LEVEL 1 FOR 1000.0;
		LEVEL 0 FOR 150471.581;
	}
}

TRANSITION_LIST("count_gatein[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 28.419;
		NODE
		{
			REPEAT = 49;
			LEVEL 1 FOR 500.0;
			LEVEL 0 FOR 500.0;
		}
		LEVEL 1 FOR 500.0;
		LEVEL 0 FOR 1000.0;
		LEVEL 1 FOR 149471.581;
	}
}

DISPLAY_LINE
{
	CHANNEL = "cs_phase";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}
💿 文件大小 436 K
👤 上传用户東狼
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#verilog #fpga #编写 #模块
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