phase_test.tan.rpt

verilog编写基于fpga的鉴相器模块

; 6.862 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[7]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[28] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.877 ns                ;
; 6.862 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[7]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.877 ns                ;
; 6.862 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[7]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[30] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.877 ns                ;
; 6.867 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[31] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.872 ns                ;
; 6.872 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[21] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.847 ns                ;
; 6.872 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[22] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.847 ns                ;
; 6.872 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[23] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.847 ns                ;
; 6.872 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[24] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.847 ns                ;
; 6.872 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[25] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.847 ns                ;
; 6.898 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[12] ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[31] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.841 ns                ;
; 6.927 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[4]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[26] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.792 ns                ;
; 6.927 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[4]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[27] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.792 ns                ;
; 6.927 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[4]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[28] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.792 ns                ;
; 6.927 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[4]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.792 ns                ;
; 6.927 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[4]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[30] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.792 ns                ;
; 6.936 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[8]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[26] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.803 ns                ;
; 6.936 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[8]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[27] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.803 ns                ;
; 6.936 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[8]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[28] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.803 ns                ;
; 6.936 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[8]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.803 ns                ;
; 6.936 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[8]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[30] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.803 ns                ;
; 6.944 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[26] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.795 ns                ;
; 6.944 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[27] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.795 ns                ;
; 6.944 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[28] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.795 ns                ;
; 6.944 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.795 ns                ;
; 6.944 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[30] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.739 ns                  ; 2.795 ns                ;
; 6.947 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[3]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[21] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.772 ns                ;
; 6.947 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[3]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[22] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.772 ns                ;
; 6.947 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[3]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[23] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.772 ns                ;
; 6.947 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[3]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[24] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.772 ns                ;
; 6.947 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[3]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[25] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.772 ns                ;
; 6.949 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[16] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.770 ns                ;
; 6.949 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[17] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.770 ns                ;
; 6.949 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[18] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.770 ns                ;
; 6.949 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[19] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.770 ns                ;
; 6.949 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[20] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.770 ns                ;
; 6.960 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[1]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[21] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.759 ns                ;
; 6.960 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[1]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[22] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.759 ns                ;
; 6.960 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[1]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[23] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.759 ns                ;
; 6.960 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[1]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[24] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.759 ns                ;
; 6.960 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[1]  ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[25] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.719 ns                  ; 2.759 ns                ;
; 6.973 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[13] ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[31] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 10.000 ns