phase_test.tan.rpt

verilog编写基于fpga的鉴相器模块

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                 ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; phase_pll:inst12|altpll:altpll_component|_clk0 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; clk      ; 2                     ; 1                   ; -1.885 ns ;              ;
; clk                                            ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; phaseinA                                       ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; phaseinB                                       ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'phase_pll:inst12|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------+------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                     ; To                                                                                       ; From Clock                                     ; To Clock                                       ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------+------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 4.530 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6]  ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.767 ns                ;
; 4.530 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[7]  ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.767 ns                ;
; 4.530 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[8]  ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.767 ns                ;
; 4.530 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[9]  ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.767 ns                ;
; 4.530 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[10] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.767 ns                ;
; 4.530 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[11] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.767 ns                ;
; 4.530 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[12] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.767 ns                ;
; 4.530 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[13] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.767 ns                ;
; 4.530 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[14] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.767 ns                ;
; 4.530 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[15] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.767 ns                ;
; 4.535 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[16] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.762 ns                ;
; 4.535 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[17] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.762 ns                ;
; 4.535 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[18] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.762 ns                ;
; 4.535 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[19] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.762 ns                ;
; 4.535 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[20] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.762 ns                ;
; 4.535 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[21] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.762 ns                ;
; 4.535 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[22] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.762 ns                ;
; 4.535 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[23] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.762 ns                ;
; 4.535 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[24] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.762 ns                ;
; 4.535 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[25] ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.297 ns                  ; 2.762 ns                ;
; 4.548 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[0]  ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.317 ns                  ; 2.769 ns                ;
; 4.548 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[1]  ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.317 ns                  ; 2.769 ns                ;
; 4.548 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2]  ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.317 ns                  ; 2.769 ns                ;
; 4.548 ns                                ; None                                                ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[3]  ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 8.115 ns                    ; 7.317 ns                  ; 2.769 ns                ;