phase_test.tan.rpt

verilog编写基于fpga的鉴相器模块

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+---------------------------------------------------------------+----------+-----------------------------------+----------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------+------------------------------------------------+--------------+
; Type                                                          ; Slack    ; Required Time                     ; Actual Time                      ; From                                                                                     ; To                                                                                       ; From Clock                                     ; To Clock                                       ; Failed Paths ;
+---------------------------------------------------------------+----------+-----------------------------------+----------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------+------------------------------------------------+--------------+
; Worst-case tsu                                                ; N/A      ; None                              ; 8.371 ns                         ; cs_phase                                                                                 ; phase_test:inst|COUNTNUM[0]                                                              ; --                                             ; clk                                            ; 0            ;
; Worst-case tco                                                ; N/A      ; None                              ; 8.332 ns                         ; phase_test:inst|COUNTNUM[29]                                                             ; phase_result[29]                                                                         ; clk                                            ; --                                             ; 0            ;
; Worst-case th                                                 ; N/A      ; None                              ; 0.153 ns                         ; gatein[14]                                                                               ; phase_test:inst|gatelim[14]                                                              ; --                                             ; clk                                            ; 0            ;
; Clock Setup: 'clk'                                            ; 0.303 ns ; 50.00 MHz ( period = 20.000 ns )  ; N/A                              ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] ; phase_test:inst|COUNTNUM[29]                                                             ; phase_pll:inst12|altpll:altpll_component|_clk0 ; clk                                            ; 0            ;
; Clock Setup: 'phase_pll:inst12|altpll:altpll_component|_clk0' ; 4.530 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; phase_test:inst|sclr                                                                     ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6]  ; clk                                            ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'phaseinB'                                       ; N/A      ; None                              ; 127.80 MHz ( period = 7.825 ns ) ; phase_test:inst|counttemp[15]                                                            ; phase_test:inst|counttemp[14]                                                            ; phaseinB                                       ; phaseinB                                       ; 0            ;
; Clock Setup: 'phaseinA'                                       ; N/A      ; None                              ; 127.80 MHz ( period = 7.825 ns ) ; phase_test:inst|counttemp[15]                                                            ; phase_test:inst|counttemp[14]                                                            ; phaseinA                                       ; phaseinA                                       ; 0            ;
; Clock Hold: 'clk'                                             ; 1.031 ns ; 50.00 MHz ( period = 20.000 ns )  ; N/A                              ; phase_test:inst|PLLEN                                                                    ; phase_test:inst|PLLEN                                                                    ; clk                                            ; clk                                            ; 0            ;
; Clock Hold: 'phase_pll:inst12|altpll:altpll_component|_clk0'  ; 1.064 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[31] ; phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[31] ; phase_pll:inst12|altpll:altpll_component|_clk0 ; phase_pll:inst12|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                                  ;          ;                                   ;                                  ;                                                                                          ;                                                                                          ;                                                ;                                                ; 0            ;
+---------------------------------------------------------------+----------+-----------------------------------+----------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------+------------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+