phase_test.fit.summary

来自「verilog编写基于fpga的鉴相器模块」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Sun Aug 19 20:49:06 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : phase_test
Top-level Entity Name : phase_control
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 118 / 5,980 ( 2 % )
Total pins : 54 / 185 ( 29 % )
Total virtual pins : 0
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 1 / 2 ( 50 % )