phase_test.map.summary

verilog编写基于fpga的鉴相器模块

Analysis & Synthesis Status : Successful - Sun Aug 19 20:48:59 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : phase_test
Top-level Entity Name : phase_control
Family : Cyclone
Total logic elements : 118
Total pins : 54
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 1