📄 usb_new_usb_int_str.vhdl
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FsClk => FsClk,
Clk12MHzRef => Clk12MHzRef,
Clk48MHz => Clk48MHz,
ConfigArray => ConfigArray_int,
RG_BusActive => RG_BusActive,
TestMode => TestMode
);
SIEINTERFACE_1: SIEINTERFACE
port map (
SIE_StartEndpSearch => SIE_StartEndpSearch,
MM_EndpSearchReady => MM_EndpSearchReady,
MM_EndpSearchSelected => MM_EndpSearchSelected,
SIE_RxEOP => SIE_RxEOP,
SIE_RxPid => SIE_RxPid,
SIE_RxPidRdy => SIE_RxPidRdy,
SIE_RxData => SIE_RxData,
SIE_RxDataRdy => SIE_RxDataRdy,
SIE_RxErrorType => SIE_RxErrorType,
SIE_RxError => SIE_RxError,
SIE_SOFByte1 => SIE_SOFByte1,
SIE_SOFByte2 => SIE_SOFByte2,
MM_TxData => MM_TxData,
MM_TxDataRdy => MM_TxDataRdy,
MM_TxData1Pid => MM_TxData1Pid,
SIE_TxDataAck => SIE_TxDataAck,
MM_Accepted => MM_Accepted,
MM_Stalled => MM_Stalled,
MM_ISO => MM_ISO,
MM_Resume => MM_Resume,
MM_NeedClock => MM_NeedClock,
TM_EOF1 => TM_EOF1,
DataToHandlers => DataToHandlers,
DataFromHandlers_In => SIEData1,
DataFromHandlers_Out => SIEData,
MM_EmbeddedBabbled => MM_EmbeddedBabbled,
SH_Succes => SH_Succes,
SH_Configured => SH_Configured,
ConfigArray => ConfigArray_int,
FsClk => FsClk,
Reset_N => Reset_N
);
SIE_1: SIE
port map (
CR_UsbLineBits => CR_UsbLineBits,
SIE_TxLogValue => SIE_TxLogValue,
SIE_UsbEnable_N => SIE_UsbEnable_N,
SIE_RxPid => SIE_RxPid,
SIE_RxPidRdy => SIE_RxPidRdy,
SIE_RxData => SIE_RxData,
SIE_RxDataRdy => SIE_RxDataRdy,
SIE_SOFByte1 => SIE_SOFByte1,
SIE_SOFByte2 => SIE_SOFByte2,
SIE_RxEOP => SIE_RxEOP,
MM_TxData1Pid => MM_TxData1Pid,
MM_TxData => MM_TxData,
MM_TxDataRdy => MM_TxDataRdy,
SIE_TxDataAck => SIE_TxDataAck,
MM_EmbeddedBabbled => MM_EmbeddedBabbled,
SIE_RxErrorType => SIE_RxErrorType,
SIE_RxError => SIE_RxError,
SIE_StartEndpSearch => SIE_StartEndpSearch,
MM_EndpSearchReady => MM_EndpSearchReady,
MM_EndpSearchSelected => MM_EndpSearchSelected,
MM_Accepted => MM_Accepted,
MM_Stalled => MM_Stalled,
MM_ISO => MM_ISO,
SIE_LowSpeedTransaction => SIE_LowSpeedTransaction,
SIE_RxSOF => SIE_RxSOF,
SIE_CREnable => SIE_CREnable,
TM_SendResume => TM_SendResume,
SIE_RxUsbLogValue => SIE_RxUsbLogValue,
ConfigArray => ConfigArray_int,
FsClk => FsClk,
Reset_N => Reset_N
);
TIMERS_SF_1: TIMERS_SF
port map (
MM_Resume => MM_Resume,
TM_SendResume => TM_SendResume,
PI_NeedClock => PI_NeedClock,
MM_NeedClock => MM_NeedClock,
EX_NeedClock => EX_NeedClock,
RG_BusActive => RG_BusActive,
TM_Suspend => TM_Suspend,
TM_Idle5ms => TM_Idle5ms,
USB_Suspended => USB_Suspended,
Suspend_In => Suspend_In,
TM_ClockOn => TM_ClockOn,
TM_ClockRestarted => TM_ClockRestarted,
RemoteWakeup => RemoteWakeup,
SIE_RxSOF => SIE_RxSOF,
TM_EOF1 => TM_EOF1,
TM_EOF2 => TM_EOF2,
FsClk => FsClk,
PUReset_N => PUReset_N,
RG_SetSE0Int => RG_SetSE0Int,
ConfigArray => ConfigArray_int,
USB_FrameClock => USB_FrameClock,
TM_IsoToggle => TM_IsoToggle_I,
TM_1kHzPulse => TM_1kHzPulse,
TestMode => TestMode
);
UC_HANDLER_1: UC_HANDLER
generic map (
ID => 0
)
port map (
DataFromUC => DataFromUC,
DataToUC_In => UCData1,
DataToUC_Out => UCData,
RG_SetSE0Int => RG_SetSE0Int,
HC_ResetDevice => HC_ResetDevice,
DH_Connect => DH_Connect_I,
DataFromHandlers_In => SIEData,
DataFromHandlers_Out => SIEData0,
DataToHandlers => DataToHandlers,
Sie_Read => Sie_Read,
Sie_Write => Sie_Write,
Uc_To_Pi => Uc_To_Pi,
Pi_To_Uc => Pi_To_Uc,
SIE_EndTransfer => SIE_EndTransfer,
RxError_SIE => RxError_SIE,
SIE_N_Data => SIE_N_Data,
Start_In_Transfer => Start_In_Transfer,
N_Data_EP => N_Data_EP,
TestMode => TestMode,
ConfigArray => ConfigArray_int,
PUReset_N => PUReset_N,
FsClk => FsClk,
EPBufferInfo => EPBufferInfo,
TM_IsoToggle => TM_IsoToggle_I
);
EP_HANDLER_1: EP_HANDLER
port map (
-- Interface to SYNCHRONIZER
If_Busy => If_Busy,
CommandCodeChannel => CommandCodeChannel,
CmdCodeValid_Out => CmdCodeValid_Out,
Trans_Enable => Trans_Enable,
Read => Read,
Data_Out => Data_Out,
EP_number => EP_number,
End_Transfer => End_Transfer,
EndTransfer_Cmd => EndTransfer_Cmd,
Rx_N_data => Rx_N_data,
USBEp0Intr_Set => USBEp0Intr_Set,
USBEp1Intr_Set => USBEp1Intr_Set,
USBEp2Intr_Set => USBEp2Intr_Set,
USBEp3Intr_Set => USBEp3Intr_Set,
USBEp4Intr_Set => USBEp4Intr_Set,
USBEp5Intr_Set => USBEp5Intr_Set,
USBEp6Intr_Set => USBEp6Intr_Set,
USBEp7Intr_Set => USBEp7Intr_Set,
USBDevIntr_Set => USBDevIntr_Set,
USBToggleBuffer => USBToggleBuffer,
UCToggleBuffer => UCToggleBuffer,
RxError => RxError,
FullBuffer_UC => FullBuffer_UC,
PI_IsoToggle => PI_IsoToggle,
CommandData => CommandData,
CmdAccept => CmdAccept,
CmdDataValid => CmdDataValid,
reg_ram_read => reg_ram_read,
reg_ram_tag => reg_ram_tag,
-- Interface to TRNSMT_RAM
Read_Req => Read_Req,
TxDest_NData => TxDest_NData,
Data_In => Data_In,
-- Interface to UC_HANDLER
DataToUC_In => UCData,
Uc_To_Pi => Uc_To_Pi,
Sie_Write => Sie_Write,
Sie_Read => Sie_Read,
SIE_EndTransfer => SIE_EndTransfer,
RxError_SIE => RxError_SIE,
Start_In_Transfer => Start_In_Transfer,
SIE_N_Data => SIE_N_Data,
EPBufferInfo => EPBufferInfo,
N_Data_EP => N_Data_EP,
Pi_To_Uc => Pi_To_Uc,
DataFromUC => DataFromUC,
DataToUC_Out => UCData0,
-- Interface to DEVICE_HANDLER
DH_Interrupt_Ep0 => DH_Interrupt_Ep0,
DH_Interrupt_Ep1 => DH_Interrupt_Ep1,
DH_Interrupt_Ep2 => DH_Interrupt_Ep2,
DH_Interrupt_Ep3 => DH_Interrupt_Ep3,
DH_Interrupt_Ep4 => DH_Interrupt_Ep4,
DH_Interrupt_Ep5 => DH_Interrupt_Ep5,
DH_Interrupt_Ep6 => DH_Interrupt_Ep6,
DH_Interrupt_Ep7 => DH_Interrupt_Ep7,
DH_Interrupt_Dev => DH_Interrupt_Dev,
-- Interface to TIMERS_SF
TM_IsoToggle => TM_IsoToggle_I,
-- clock and reset from system
FsClk => FsClk,
Reset_N => Reset_N
);
PVCI_ENG_1 : PVCI_ENG
port map (
-- Interface to EP_HANDLER
Trans_Enable => Trans_Enable,
Read => Read,
EP_number => EP_number,
Data_Out => Data_Out,
End_Transfer => End_Transfer,
EndTransfer_Cmd => EndTransfer_Cmd,
USBEp0Intr_Set => USBEp0Intr_Set,
USBEp1Intr_Set => USBEp1Intr_Set,
USBEp2Intr_Set => USBEp2Intr_Set,
USBEp3Intr_Set => USBEp3Intr_Set,
USBEp4Intr_Set => USBEp4Intr_Set,
USBEp5Intr_Set => USBEp5Intr_Set,
USBEp6Intr_Set => USBEp6Intr_Set,
USBEp7Intr_Set => USBEp7Intr_Set,
USBDevIntr_Set => USBDevIntr_Set,
USBToggleBuffer => USBToggleBuffer,
UCToggleBuffer => UCToggleBuffer,
FullBuffer_UC => FullBuffer_UC,
PI_IsoToggle => PI_IsoToggle,
RxError => RxError,
reg_ram_read => reg_ram_read,
reg_ram_tag => reg_ram_tag,
CommandData => CommandData,
CmdDataValid => CmdDataValid,
CmdAccept => CmdAccept,
CommandCodeChannel => CommandCodeChannel,
CmdCodeValid_Out => CmdCodeValid_Out,
If_Busy => If_Busy,
Read_Req => Read_Req,
Data_In => Data_In,
TxDest_NData => TxDest_NData,
Rx_N_data => Rx_N_data,
-- Interface to RX RAM
RxRAM_DQ_In => RxRAM_DQ_In,
RxRAM_E_N => RxRAM_E_N,
RxRAM_W_N => RxRAM_W_N,
RxRAM_G_N => RxRAM_G_N,
RxRAM_A => RxRAM_A,
RxRAM_DQ_Out => RxRAM_DQ_Out,
-- Interface to TX RAM
TxRAM_E_N => TxRAM_E_N,
TxRAM_W_N => TxRAM_W_N,
TxRAM_G_N => TxRAM_G_N,
TxRAM_A => TxRAM_A,
TxRAM_DQ_In => TxRAM_DQ_In,
TxRAM_DQ_Out => TxRAM_DQ_Out,
-- Interrupt signals to system
Intr_Request_Irq => Intr_Request_Irq,
Intr_Request_Fiq => Intr_Request_Fiq,
-- Interface to APB
clk => clk,
pvci_reset_n => pvci_reset_n,
req => req,
address => address,
rnw => rnw,
w_data => w_data,
gnt => gnt,
r_data => r_data,
error => error
);
UPSTREAMLED_1: UPSTREAMLED
port map (
Configured_LED => Configured_LED,
SH_Succes => SH_Succes,
SH_Configured => SH_Configured,
TM_Suspend => TM_Suspend,
TM_1kHzPulse => TM_1kHzPulse,
ConfigArray => ConfigArray_int,
FsClk => FsClk,
Reset_N => Reset_N
);
ConfigArray <= ConfigArray_int;
end STR;
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