usb_new_usb_int_str.vhdl

实现USB接口功能的VHDL和verilog完整源代码

           reg_ram_tag:       out   Int_EndPointType;     -- Physical endpoint number

           -- Interface to TRNSMT_RAM module
           Read_Req:           in   one_bit;              -- Data available in GIF.   
           TxDest_NData:       in   nine_bits;            -- Number of bytes for IN packet

           -- Interface to UC_HANDLER module

           DataToUC_In:        in    T_Handlers_to_UC;
           Uc_To_Pi:           in    T_UC_to_pi_handler;
           Sie_Write:          in    one_bit;
           Sie_Read:           in    one_bit;
           SIE_EndTransfer:    in    one_bit;
           RxError_SIE:        in    boolean; 
           Start_In_Transfer:  in    one_bit;
           SIE_N_Data:         in    integer range 0 to MAX_OVERFLOW_SIZE;
           EPBufferInfo:       in    T_EPBufferInfo;
           N_Data_EP:         out    nine_bits;
           Pi_To_Uc:          out    T_pi_to_uc_handler;
           DataFromUC:        out    T_UC_to_Handlers;
           DataToUC_Out:      out    T_Handlers_to_UC;
           
           -- Interface to DEVICE_HANDLER module

           DH_Interrupt_Ep0:   in    boolean;           
           DH_Interrupt_Ep1:   in    boolean;
           DH_Interrupt_Ep2:   in    boolean;           
           DH_Interrupt_Ep3:   in    boolean;
           DH_Interrupt_Ep4:   in    boolean;           
           DH_Interrupt_Ep5:   in    boolean;
           DH_Interrupt_Ep6:   in    boolean;           
           DH_Interrupt_Ep7:   in    boolean;
           DH_Interrupt_Dev:   in    boolean;           

           -- Interface to TIMERS_SF module

           TM_IsoToggle:       in    integer range 0 to 1;

           -- clock and reset from system     

           FsClk:             in     one_bit;
           Reset_N:           in     std_logic
          );           
END component;

component PVCI_ENG
   port (
       -- Interface to EP_HANDLER modlue

       Trans_Enable:          in   one_bit;              -- Data transfer enable
       Read:                  in   one_bit;              -- '1' read data
       EP_number:             in   Int_EndPointType;     -- Physical endpoint number
       Data_Out:              in   byte;                 -- Data bus for OUT endpoints
       End_Transfer:          in   one_bit;              -- End of transfer for packet data 
       EndTransfer_Cmd:       in   one_bit;              -- End of transfer for command data
       USBEp0Intr_Set:        in   one_bit;              -- USB Ep0 interrupt
       USBEp1Intr_Set:        in   one_bit;              -- USB Ep1 interrupt
       USBEp2Intr_Set:        in   one_bit;              -- USB Ep2 interrupt
       USBEp3Intr_Set:        in   one_bit;              -- USB Ep3 interrupt
       USBEp4Intr_Set:        in   one_bit;              -- USB Ep4 interrupt
       USBEp5Intr_Set:        in   one_bit;              -- USB Ep5 interrupt
       USBEp6Intr_Set:        in   one_bit;              -- USB Ep6 interrupt
       USBEp7Intr_Set:        in   one_bit;              -- USB Ep7 interrupt
       USBDevIntr_Set:        in   one_bit;              -- USB Dev interrupt

       USBToggleBuffer:       in   T_ToggleArray;        -- USB buffer toggle 
       UCToggleBuffer:        in   T_ToggleArray;        -- UC buffer toggle
       FullBuffer_UC:         in   T_Full;               -- Buffer full for endpoints
       PI_IsoToggle:          in   integer range 0 to 1; -- ISO buffer toggle
       RxError:               in   boolean;              -- Error in packet transfer
       reg_ram_read:          in   one_bit;              -- Start of IN transfer
       reg_ram_tag:           in   Int_EndPointType;     -- Physical endpoint number
       CommandData:           in   byte;                 -- Command data
       CmdDataValid:          in   boolean;              -- Command data valid
       CmdAccept:             in   boolean;              -- Handshake signal for Command accepted
       CommandCodeChannel:    out  eleven_bits;          -- Command code
       CmdCodeValid_Out:      out  boolean;              -- Command code valid
       If_Busy:               out  boolean;              -- Interface busy
       Read_Req:              out  one_bit;              -- ????
       Data_In:               out  byte;                 -- Data bus for IN data
       TxDest_NData:          out  nine_bits;            -- Number of bytes for IN packet
       Rx_N_data:             in   integer range 0 to MAX_OVERFLOW_SIZE; -- Packet size
       
       -- Interface to RAM module

       RxRAM_DQ_In:           in   four_bytes;           -- RAM data in-bus (32-bits)
       RxRAM_E_N:             out  one_bit;              -- RAM enable, active low
       RxRAM_W_N:             out  one_bit;              -- RAM write, active low
       RxRAM_G_N:             out  one_bit;              -- RAM grant(read), active low
       RxRAM_A:               out  RxRAMAddr_bits;       -- RAM address bus (??-bits)
       RxRAM_DQ_Out:          out  four_bytes;           -- RAM data out-bus(32-bits)
       
       -- Interface to TRNSMT_RAM module

       TxRAM_E_N:             out  one_bit;              -- RAM enable, active low
       TxRAM_W_N:             out  one_bit;              -- RAM write, active low
       TxRAM_G_N:             out  one_bit;              -- RAM grant(read), active low
       TxRAM_A:               out  TxRAMAddr_bits;       -- RAM address bus
       TxRAM_DQ_In:           in   four_bytes;           -- RAM data in-bus
       TxRAM_DQ_Out:          out  four_bytes;           -- RAM data out-bus
       
       -- Interrupt signals

       Intr_Request_Irq:      out one_bit;               -- All Interrupt request to processor
       Intr_Request_Fiq:      out one_bit;               -- Frame Interrupt request to processor
       
       -- Interface to APB_WRAPPER module
                     
       clk:                   in  one_bit;               -- PVCI clock
       pvci_reset_n:          in  one_bit;               -- Reset
       req:                   in  one_bit;               -- Request
       address:               in  byte;                  -- Address
       rnw:                   in  one_bit;               -- '0' write, '1' read
       w_data:                in  four_bytes;            -- Write data
       gnt:                   out one_bit;               -- Grant
       r_data:                out four_bytes;            -- Read data
       error:                 out one_bit                -- Error 

         );
END component  ; 

component UPSTREAMLED
  port    (
          Configured_LED:           out one_bit;
          SH_Succes:                 in boolean;
          SH_Configured:             in boolean;
          TM_Suspend:                in boolean;
          TM_1kHzPulse:              in one_bit;
          ConfigArray:               in S_ConfigArray;
          FsClk:                     in one_bit;
          Reset_N:                   in one_bit
          );
end component;

signal CR_UsbLineBits: two_bits;
signal ConfigArray_int: S_ConfigArray;
signal DataFromUC: T_UC_to_Handlers;
signal DataToHandlers: T_SIE_to_Handlers;
signal DH_Connect_I: boolean;
signal MM_Accepted: boolean;
signal MM_EmbeddedBabbled: boolean;
signal MM_EndpSearchReady: boolean;
signal MM_EndpSearchSelected: boolean;
signal MM_ISO: boolean;
signal MM_NeedClock: boolean;
signal MM_Resume: boolean;
signal MM_Stalled: boolean;
signal MM_TxData: S_UsbWord_bits;
signal MM_TxData1Pid: boolean;
signal MM_TxDataRdy: boolean;
signal PI_NeedClock: boolean;
signal PUReset_N: one_bit;
signal RG_BusActive: boolean;
signal RG_SetSE0Int: boolean;
signal Reset48MHz_N: one_bit;
signal Reset_N: one_bit;
signal SH_Configured: boolean;
signal SH_Succes: boolean;
signal SIEData: T_Handlers_to_SIE;
signal SIEData0: T_Handlers_to_SIE;
signal SIEData1: T_Handlers_to_SIE;
signal SIE_CREnable: boolean;
signal SIE_RxData: S_UsbWord_bits;
signal SIE_RxDataRdy: boolean;
signal SIE_RxEOP: boolean;
signal SIE_RxError: boolean;
signal SIE_RxErrorType: T_PACKET_ERROR_enum;
signal SIE_RxPid: T_Pid_enum;
signal SIE_RxPidRdy: boolean;
signal SIE_RxSOF: boolean;
signal SIE_SOFByte1: boolean;
signal SIE_SOFByte2: boolean;
signal SIE_StartEndpSearch: boolean;
signal SIE_TxDataAck: boolean;
signal TM_1kHzPulse: one_bit;
signal TM_EOF1: boolean;
signal TM_SendResume: boolean;
signal TM_Suspend: boolean;
signal TM_RemoteWakeupEvent: boolean;
signal UCData: T_Handlers_to_UC;
signal UCData0: T_Handlers_to_UC;
signal UCData1: T_Handlers_to_UC;
signal If_Busy  :  boolean; -- GIF is 
signal Read_Req : one_bit;
signal core_wait : boolean;
signal RxError_SIE:  boolean;	   
signal SIE_N_Data:  integer range 0 to MAX_OVERFLOW_SIZE;
signal Data_Ready : one_bit;
signal Trans_Enable   : one_bit;
signal Read   : one_bit;
signal Data_In    :   byte;
signal Data_Out   :  byte;
signal End_Transfer   : one_bit;
signal Sie_Read: one_bit;
signal Sie_Write: one_bit;
signal Uc_To_Pi : T_UC_to_pi_handler;
signal Pi_To_Uc : T_Pi_To_Uc_handler;
signal SIE_EndTransfer :  one_bit;
signal Start_In_Transfer  :  one_bit; 
signal Rx_N_data:   integer range 0 to MAX_OVERFLOW_SIZE;
signal N_Data_EP   : nine_bits;
signal EPBufferInfo: T_EPBufferInfo;
--signal USBCoreIntr_Set: one_bit;
signal USBEp0Intr_Set: one_bit;
signal USBEp1Intr_Set: one_bit;
signal USBEp2Intr_Set: one_bit;
signal USBEp3Intr_Set: one_bit;
signal USBEp4Intr_Set: one_bit;
signal USBEp5Intr_Set: one_bit;
signal USBEp6Intr_Set: one_bit;
signal USBEp7Intr_Set: one_bit;
signal USBDevIntr_Set: one_bit;
--signal DH_Interrupt_I: boolean;
signal DH_Interrupt_Ep0: boolean;
signal DH_Interrupt_Ep1: boolean;
signal DH_Interrupt_Ep2: boolean;
signal DH_Interrupt_Ep3: boolean;
signal DH_Interrupt_Ep4: boolean;
signal DH_Interrupt_Ep5: boolean;
signal DH_Interrupt_Ep6: boolean;
signal DH_Interrupt_Ep7: boolean;
signal DH_Interrupt_Dev: boolean;
signal USBToggleBuffer: T_ToggleArray;
signal EndTransfer_Cmd: one_bit;
signal RxError: boolean;
signal TxDest_NData: nine_bits;
signal UCToggleBuffer: T_ToggleArray;
signal FullBuffer_UC: T_Full;
signal TM_IsoToggle_I: integer range 0 to 1;
signal PI_IsoToggle: integer range 0 to 1;
signal CommandData: byte;
signal CommandCodeChannel: eleven_bits;
signal CmdAccept: boolean;
signal CmdDataValid: boolean;
signal CmdCodeValid_Out: boolean;
signal reg_ram_read: one_bit;
signal reg_ram_tag: Int_EndpointType;
signal EP_number: Int_EndPointType;

begin

DH_Connect <= DH_Connect_I;
TM_IsoToggle <= TM_IsoToggle_I;

CLKREC_1: CLKREC
  port map    (
              HB_UsbDifBit               => HB_UsbDifBit,
              HB_UsbLineBits             => HB_UsbLineBits,
              CR_UsbLineBits             => CR_UsbLineBits,
              CR_DebugRecDataP           => CR_DebugRecDataP,
              CR_DebugRecDataN           => CR_DebugRecDataN,
              Clk12MHz_O                 => Clk12MHz_O,
              Clk12MHzRef_O              => Clk12MHzRef_O,
              SIE_CREnable               => SIE_CREnable,
              TM_Suspend                 => TM_Suspend,
              Clk48MHz                   => Clk48MHz,
              Reset48MHz_N               => Reset48MHz_N,
              PU_Reset_N                 => PU_Reset_N
              );

DEVICE_HANDLER_1: DEVICE_HANDLER
  generic map (
              ID                         => 1
              )
  port map    (
              DataToHandlers             => DataToHandlers,
              DataFromHandlers_In        => SIEData0,
              DataFromHandlers_Out       => SIEData1,
              DataFromUC                 => DataFromUC,
              DataToUC_In                => UCData0,
              DataToUC_Out               => UCData1,
              VBusAvailable              => VBusAvailable,
              DH_Connect                 => DH_Connect_I,
              TM_1kHzPulse               => TM_1kHzPulse,
              ChipID                     => ChipID,
              ConfigArray                => ConfigArray_int,
              PINConfigArray             => PINConfigArray,
              DH_Interrupt_Ep0           => DH_Interrupt_Ep0,
              DH_Interrupt_Ep1           => DH_Interrupt_Ep1,
              DH_Interrupt_Ep2           => DH_Interrupt_Ep2,
              DH_Interrupt_Ep3           => DH_Interrupt_Ep3,
              DH_Interrupt_Ep4           => DH_Interrupt_Ep4,
              DH_Interrupt_Ep5           => DH_Interrupt_Ep5,
              DH_Interrupt_Ep6           => DH_Interrupt_Ep6,
              DH_Interrupt_Ep7           => DH_Interrupt_Ep7,
              DH_Interrupt_Dev           => DH_Interrupt_Dev,
              RG_SetSE0Int               => RG_SetSE0Int,
              TM_Suspend                 => TM_Suspend,
              TM_RemoteWakeupEvent       => TM_RemoteWakeupEvent,
              FsClk                      => FsClk,
              PUReset_N                  => PUReset_N
              );

RGEN_1: RGEN
  port map    (
              USB_Reset_O_N              => USB_Reset_O_N,
              RG_SetSE0Int               => RG_SetSE0Int,
              RG_BUSReset                => RG_BUSReset,
              Reset_N                    => Reset_N,
              PUReset_N                  => PUReset_N,
              Reset12MHzRef_N            => Reset12MHzRef_N,
              Reset48MHz_N               => Reset48MHz_N,
              UP_DsLineBits              => UP_DsLineBits,
              PU_Reset_N                 => PU_Reset_N,