usb_new_usb_cntrl_rtl.vhdl

实现USB接口功能的VHDL和verilog完整源代码

               end loop;
          when others =>
               fiqstatus_var := '0';
               for i in 0 to N_intrbits loop
                   irqstatus_var := irqstatus_var or (Intr_Status_Reg(i) and Intr_Enable_Reg(i));
               end loop; 
       end case;     
       Intr_Request_Irq <= irqstatus_var;
       Intr_Request_Fiq <= fiqstatus_var;
    end InterruptController;
    -----------------------------------------------------------------------------------   
    begin   
    if(clk'event and clk = '1') then
       --Resetting of Registers.
       if(pvci_reset_n = '0') then         
          Cmd_Code_Reg          <= (others => '0');
          Cmd_Data_Reg          <= (others => '0');
          Tramsmt_Data_Reg      <= (others => '0');
          Intr_Status_Reg       <= (others => '0');
          Intr_Enable_Reg       <= (others => '0');
          TxPkt_Lngth_Reg       <= (others => '0');
          RxPkt_Lngth_Reg       <= (others => '0');
          Usb_Cntrl_Reg         <= (others => '0');
          Fiq_Sel_Reg           <= (others => '0');
          Cmd_Code_Reg_Full     <= '0';
          Cmd_Data_Reg_full     <= '0';
          Receive_Data_Reg_Full <= '0' ;
          Trnsmt_Data_Reg_Full  <= '0' ; 
          Rx_Pkt_End_I          <= '0';
          Read_Enable_Q         <= '0';
          Write_Enable_Q        <= '0'; 
          Packet_Length         <= (others => '0');
          Tx_Pkt_End_I          <= '0';
          EndPaktIn_IntrSet     <= '0';
          Write_Enable          <= '0';
          Tx_Pkt_End_Q          <= '0';
          CmdCodeEmpty_IntrSet  <= '0';
          CmdDataFull_IntrSet   <= '0';
          EndPaktOut_IntrSet    <= '0';
          Rd_data               <= (others => '0');
	  Read_Enable_I         <= '0';
       else
          Read_Enable_Q    <= Read_Enable;
          Write_Enable_Q   <= Write_Enable;
          Tx_Pkt_End_Q     <= Tx_Pkt_End_I;
          
          -- Writing to FIQ Sel Register
          if(Write_Fiq_Sel = '1') then
             Fiq_Sel_Reg <= Wr_Data(2 downto 0);
          end if;
          
	  -- Writing to command code register
          if(Write_Cmd_Code = '1') then
             Cmd_Code_Reg(2 downto 0)   <= Wr_Data(10 downto 8);
             Cmd_Code_Reg(10 downto 3)  <= Wr_Data(23 downto 16);
             Cmd_Code_Reg_Full <= '1';
          end if;   

	  -- Writing to transmit data register and update the packet lenght register
          if(Write_Transmt_Data = '1') then
             Tramsmt_Data_Reg <= Wr_Data;
             Trnsmt_Data_Reg_Full <= '1';
             if(TxPkt_Lngth_Reg > 4) then
                TxPkt_Lngth_Reg <= TxPkt_Lngth_Reg - 4;
             else
                TxPkt_Lngth_Reg <= (others => '0') ;
		EndPaktIn_IntrSet <= '1';
		Write_Enable      <= '0';
             end if;         
          end if;

	  -- Writing to tx packet length register
          if(Write_TxPkt_Lngth = '1') then
             TxPkt_Lngth_Reg <= Wr_Data(9 downto 0);
             Packet_Length   <= Wr_Data(9 downto 0);
          end if;

	  -- Read from tx packet length register
          if(Read_TxPkt_Lngth = '1') then
             Rd_Data(9 downto 0)   <= TxPkt_Lngth_Reg;
             Rd_Data(31 downto 10) <= (others => '0');
          end if;

	  -- Writing to USB control register
          if(Write_Usb_Cntrl = '1') then
             Usb_Cntrl_Reg <= Wr_Data(5 downto 0);
             Write_Enable <= Wr_Data(1);
             Read_Enable_I  <= Wr_Data(0);
          end if;
            
          -- Reading from Usb Control register
          if(Read_Usb_Cntrl = '1') then
             Rd_Data(5 downto 0)  <= Usb_Cntrl_Reg;
             Rd_Data(31 downto 6) <= (others => '0');
          end if;
          
          -- Reading from Interrupt enable register
          if(Read_Intr_Enable = '1') then
             Rd_Data(13 downto 0)  <= Intr_Enable_Reg;
             Rd_Data(31 downto 14) <= (others => '0');
          end if;
          
          -- Read from Interrupt status register
          if(Read_Intr_Status = '1') then
             Rd_data(19 downto 0)  <= Intr_Status_Reg;
             Rd_Data(31 downto 20) <= (others => '0');
          end if;
          
          -- Read from Command Data register
          if(Read_Cmd_Data = '1') then
             Rd_data(7 downto 0)  <= Cmd_Data_Reg;
             Rd_Data(31 downto 8) <= (others => '0');
          end if;
          
          -- Reading from rx packet length register
          if(Read_RxPkt_Lngth = '1') then
             Rd_Data(10 downto 0)  <= RxPkt_Lngth_Reg;
             Rd_Data(31 downto 11)  <= (others => '0');
          end if;
          
          -- If any address selected by processor does not exist in
          -- USB device inform the processor by "DEADABBA"
          if(Error = '1') then
             Rd_Data <= WRONG_ADDRESS_ID;
          end if;
          
	  -- Reading from receive data register
          if(Read_Receive_Data = '1' and Read_Enable = '1' ) then
             Rd_Data <= Receive_Data_Reg;
             Receive_Data_Reg_Full <= '0';
             if(RxPkt_Lngth_Reg(9 downto 0) > 4) then
                RxPkt_Lngth_Reg(9 downto 0) <= RxPkt_Lngth_Reg(9 downto 0) - 4;
             else
                RxPkt_Lngth_Reg <= (others => '0');
                Read_Enable_I  <= '0';
                Usb_Cntrl_Reg(0) <= '0';
		EndPaktOut_IntrSet <= '1';
             end if;
          end if;   
          
          -- Reading from the receive RAM block
          if(Receive_Data_Reg_Full = '0' and Read_Enable = '1' ) then
             Receive_Data_Reg_Full <= '1';
          end if;
          -- Writing into Rx_pkt_length reg
          if(write_pkt_length) then
             RxPkt_Lngth_Reg(9 downto 0) <= Receive_Data_Reg(9 downto 0);
             RxPkt_Lngth_Reg(10) <= Receive_Data_Reg(31);
             Receive_Data_Reg_Full <= '0';
          end if;
          
          -- Writing into Trnsmt Ram block
          if(Trnsmt_Data_Reg_Full = '1' and Usb_Cntrl_Reg(1) = '1' ) then
             Trnsmt_Data_Reg_Full <=  '0';
          end if;
          
          -- Assert end of packet if Read_enable goes down
          if(Read_Enable_Q = '1' and Read_Enable = '0') then
             Rx_Pkt_End_I <= '1' ;
             Receive_Data_Reg_Full <= '0';
          end if;

          -- Reset Packet end Flag
          if(Rx_Pkt_End_I = '1') then
             Rx_Pkt_End_I <= '0';
          end if; 

	  -- Assert end of packet if Write_enable goes down
          if(Write_Enable_Q = '1' and Write_Enable = '0') then
             Tx_Pkt_End_I <= '1' ;
          end if;

          -- Reset Packet end Flag 
          if(Tx_Pkt_End_I = '1') then
             Tx_Pkt_End_I <= '0';
          end if;
          
          -- Command handling sending command code
          if(Cmd_Code_Reg_Full = '1' and CmdAccept_Out) then
             CmdCodeEmpty_IntrSet <= '1' ;
             Cmd_Code_Reg_Full <= '0';               
             CmdCodeValid_I <= false;                
          end if;
          if(CmdDataValid_Out) then
             Cmd_Data_Reg <= CommandDataChannel;
          elsif(EndTransfer_Cmd_D = '1') then
             CmdDataFull_IntrSet <= '1';     
          end if;
          if(CmdCodeEmpty_IntrSet = '1') then
	     CmdCodeEmpty_IntrSet <= '0';
          end if;
	  if(CmdDataFull_IntrSet = '1') then
	     CmdDataFull_IntrSet <= '0';
          end if;
          if(EndPaktOut_IntrSet = '1') then
	     EndPaktOut_IntrSet <= '0';
          end if;
          if(EndPaktIn_IntrSet = '1') then
	     EndPaktIn_IntrSet <= '0';
          end if;
          
          InterruptController;
       end if;
    end if;
  end process;
end RTL;