📄 usb_new_vsc9_ram_addressor.vhd
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-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is usb_new.vhd
-- -----------------------------------------------------------------------------
-- Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
--
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips. This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
--
-- -----------------------------------------------------------------------------
-- USBFS22 Device Version 1.0
-- -----------------------------------------------------------------------------
-- usb_new/data/USBFS22/RTL/usb_new_vsc9_ram_addressor.vhd : RTL VHDL
--
-- Compiled by arkrish on Tue Apr 3 17:23:42 2001
-- -----------------------------------------------------------------------------
-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Parameters: counter -b7 -t0 -p0 -f2 -L0 -C -c -S -N -M -n 0x5f -l vsc983 -padlib cxxx_iolib -Synopsys -nrtl -nentity -nadd_p -ntiming -vhdl -verilog -Rarch RTL -Sarch STRUCTURAL -br 0,4,8,12,32,48 -ipnoprompt -ipchance medium
-- vsc9_ram_addressor: 130.00 physical gates (vsc983)
-- vsc9_ram_addressor: 3370.90 squm area (vsc983)
-- -----------------------------------------------------------------------------
-- Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
--
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips. This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
--
-- -----------------------------------------------------------------------------
-- Counter Function Compiler Version 1.1d
-- -----------------------------------------------------------------------------
-- vsc9_ram_addressor : RTL & structural VHDL
-- (RTL is optimized for simulation, not synthesis)
--
-- Compiled by arkrish on Tue Apr 3 11:53:41 2001
-- -----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--synopsys translate_off
-- if trouble set hdlin_translate_off_skip_text = true
----use work.hdli.all;
library VLSI_DIVhdl;
use VLSI_DIVhdl.vlsidivhdl_package.all;
--synopsys translate_on
library work;
use work.hdli.all;
entity vsc9_ram_addressor is
port ( clk : in STD_LOGIC;
csn : in STD_LOGIC;
cen : in STD_LOGIC;
up : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(6 downto 0);
tci : out STD_LOGIC);
end vsc9_ram_addressor;
architecture STRUCTURAL of vsc9_ram_addressor is
component ni01d2
port ( i : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component nd02d2
port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
zn : out STD_LOGIC);
end component;
component in01d2
port ( i : in STD_LOGIC;
zn : out STD_LOGIC);
end component;
component an03d1
port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
a3 : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component xn02d1
port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
zn : out STD_LOGIC);
end component;
component xo02d1
port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component dfntnq1
port ( d : in STD_LOGIC;
cp : in STD_LOGIC;
q : out STD_LOGIC);
end component;
component an02d1
port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component mx21d1
port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
s : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component nr03d1
port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
a3 : in STD_LOGIC;
zn : out STD_LOGIC);
end component;
component nr04d1
port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
a3 : in STD_LOGIC;
a4 : in STD_LOGIC;
zn : out STD_LOGIC);
end component;
component nr02d1
port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
zn : out STD_LOGIC);
end component;
component nd02d1
port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
zn : out STD_LOGIC);
end component;
component nd04d1
port ( a1 : in STD_LOGIC;
a3 : in STD_LOGIC;
a4 : in STD_LOGIC;
a2 : in STD_LOGIC;
zn : out STD_LOGIC);
end component;
signal n000074 : STD_LOGIC;
signal n000046 : STD_LOGIC;
signal n000047 : STD_LOGIC;
signal n000049 : STD_LOGIC;
signal n000050 : STD_LOGIC;
signal n000052 : STD_LOGIC;
signal n000053 : STD_LOGIC;
signal n000055 : STD_LOGIC;
signal n000056 : STD_LOGIC;
signal n000058 : STD_LOGIC;
signal n000059 : STD_LOGIC;
signal n000061 : STD_LOGIC;
signal n000062 : STD_LOGIC;
signal n000063 : STD_LOGIC;
signal n000020 : STD_LOGIC;
signal n000003 : STD_LOGIC;
signal n000042 : STD_LOGIC;
signal n000041 : STD_LOGIC;
signal n000040 : STD_LOGIC;
signal n000039 : STD_LOGIC;
signal n000038 : STD_LOGIC;
signal n000037 : STD_LOGIC;
signal n000036 : STD_LOGIC;
signal n000035 : STD_LOGIC;
signal n000034 : STD_LOGIC;
signal n000033 : STD_LOGIC;
signal n000032 : STD_LOGIC;
signal n000031 : STD_LOGIC;
signal n000030 : STD_LOGIC;
signal n000029 : STD_LOGIC;
signal n000028 : STD_LOGIC;
signal n000027 : STD_LOGIC;
signal n000026 : STD_LOGIC;
signal n000025 : STD_LOGIC;
signal n000024 : STD_LOGIC;
signal n000023 : STD_LOGIC;
signal n000022 : STD_LOGIC;
signal n000021 : STD_LOGIC;
signal n000018 : STD_LOGIC;
signal n000017 : STD_LOGIC;
signal n000016 : STD_LOGIC;
signal n000015 : STD_LOGIC;
signal n000014 : STD_LOGIC;
signal n000013 : STD_LOGIC;
signal n000012 : STD_LOGIC;
signal n000011 : STD_LOGIC;
signal n000010 : STD_LOGIC;
signal n000009 : STD_LOGIC;
signal n000008 : STD_LOGIC;
signal n000007 : STD_LOGIC;
signal n000006 : STD_LOGIC;
signal n000005 : STD_LOGIC;
signal n000004 : STD_LOGIC;
signal n000002 : STD_LOGIC;
signal n000001 : STD_LOGIC;
signal vdd : STD_LOGIC;
signal vss : STD_LOGIC;
begin
vdd <= '1';
vss <= '0';
n000001 <= clk;
n000002 <= csn;
n000003 <= cen;
n000004 <= up;
q(6) <= n000011;
q(5) <= n000010;
q(4) <= n000009;
q(3) <= n000008;
q(2) <= n000007;
q(1) <= n000006;
q(0) <= n000005;
tci <= n000012;
u000001: an02d1
port map (a1 => n000017,
a2 => n000016,
z => n000018);
u000002: an02d1
port map (a1 => n000049,
a2 => n000047,
z => n000046);
u000003: an02d1
port map (a1 => n000052,
a2 => n000050,
z => n000049);
u000004: an02d1
port map (a1 => n000055,
a2 => n000053,
z => n000052);
u000005: an02d1
port map (a1 => n000058,
a2 => n000056,
z => n000055);
u000006: an02d1
port map (a1 => n000061,
a2 => n000059,
z => n000058);
u000007: an02d1
port map (a1 => n000003,
a2 => n000062,
z => n000061);
u000008: an02d1
port map (a1 => n000035,
a2 => n000074,
z => n000042);
u000009: an02d1
port map (a1 => n000031,
a2 => n000074,
z => n000040);
u000010: an02d1
port map (a1 => n000029,
a2 => n000074,
z => n000039);
u000011: an02d1
port map (a1 => n000027,
a2 => n000074,
z => n000038);
u000012: an02d1
port map (a1 => n000025,
a2 => n000074,
z => n000037);
u000013: an02d1
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